Structure and process of manufacture of split gate flash memory

Details Structure and process of manufacture of split gate flash memory Structure and process of manufacture of split gate flash memory

1995-06-23

1997-03-25

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257319, H01L 29788

Patent

active

056147465

ABSTRACT:
A method is provided for fabricating a split gate flash EPROM device. A stack is formed of a first dielectric layer on the lightly doped semiconductor substrate followd by a floating gate, a first intergate dielectric layer, an intermediate control gate layer, an isolating layer over the intermediate control gate layer, and a floating gate mask on the device. The stack is formed by etching in the pattern of the floating gate. A split gate mask is formed followed by ion implanting dopant into source/drain regions in the substrate adjacent to the mask with one source/drain region self aligned with the stack and the other spaced away from the other side of the stack. After mask removal, a second intergate dielectric layer blanket is formed with an etch back forming sidewalls next to the stack by etching away exposed portions of the first dielectric layer, forming a second dielectric layer on the substrate and the source/drain regions. Removal of the isolating layer over the intermediate control gate layer follows. Then a blanket control gate layer over the device and a control gate mask are formed, patterning the control gate layer by etching portions of the control gate layer unprotected by the control gate mask, and removal of the control gate mask.

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