Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
1999-12-23
2001-09-18
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S108000, C438S118000
Reexamination Certificate
active
06291272
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to packaging for integrated circuits. More particularly, the present invention relates to a structure and process for manufacturing substrate packages for high frequency application.
As substrate packages for integrated circuits on semiconductor chips become denser and faster, there has been a significant increase in the requirements that the substrate packages need to meet. For example the substrate packages designed for microwave applications involve high power density chips and interconnections requiring high currents. This imposes severe restrictions in terms of thermal management and also current carrying capability, on these substrate packages. The substrate packages aimed at applications especially in communications need to be thin and highly brazable. Also, certain electrical design requirements dictate that the backside of the substrate packages be metallized for providing a ground cage and slot line type transmission lines by embedding large area metal features in the dielectric layer. The substrate packages for digital applications require denser wiring and finer features (lines and via holes) to be incorporated at lower costs. It is advantageous if these substrate packages would be available in various coefficient of thermal expansions ranging from 3×10
−6
to 18×10
−6
C
−1
expanding their application space. There is also a strong drive to reduce the defect density in both the chip carriers and in the passive components in the substrate packages.
The conventional method to build such substrate packages (SCM's and MCM's) utilizes multi-layer-ceramic (MLC) processing. This involves making green sheets from the dielectric powder of choice, screening those green sheets with paste(s) of selected metallization to produce patterns and through sheet connections, or vias, stacking these screened green sheets, laminating the green sheets, and then sintering the green sheets to form a three-dimensionally connected substrate package. Sintering large size substrate packages with the very high metal loading, typically required for the communications packages, creates considerable difficulties in controlling the shrinkage, distortion and flatness of substrate packages at the end of the process. Special processing steps have to be added to assure the flatness of the substrate packages. Also, the backside metallization required to build conventional substrate packages is done by a combination of physical deposition methods and electroplating. The high tolerance required for fabricating substrate packages with very fine features cannot be increased beyond a certain limit due to the distortion of green sheets during various processing steps. Overall processing costs of the substrate packages produced using MLC techniques are relatively higher because of the longer cycle times. Therefore there is a need to develop cost effective ways to produce such substrate packages.
BRIEF SUMMARY OF THE INVENTION
An aspect of the present invention is a process for fabricating a microelectronic structure. The process comprises processing a metal carrier having a top surface and a bottom surface, wherein the top surface and the bottom surface are processed to promote; adhesion, forming a dielectric layer around the metal carrier, wherein the dielectric layer substantially covers the top surface and the bottom surface of the metal carrier, and applying a first patterned layer of conductive material to the microelectronic structure. In one preferred embodiment, the process further comprises sintering the metal carrier, the dielectric layer, and the first patterned layer of conductive material. In one preferred embodiment, the process further comprises forming a via hole through the metal carrier before the forming of the dielectric layer around the metal carrier, wherein the forming of the dielectric layer comprises forming the dielectric layer inside the via hole.
Another aspect of the present invention is a microelectronic structure comprising a metal carrier having a top surface and a bottom surface, a dielectric layer formed around the metal carrier, the dielectric layer substantially covering the top surface and the bottom surface of the metal carrier, and a first patterned layer of conductive material overlying the dielectric layer. In one preferred embodiment, the first pattern layer of conductive material overlies the metal carrier. These and other aspects of the invention will become apparent upon a review of the following detailed description of the presently preferred embodiments of the invention, when viewed in conjunction with the appended drawings.
REFERENCES:
patent: 5229727 (1993-07-01), Clark et al.
patent: 5232548 (1993-08-01), Ehrenberg et al.
patent: 5389904 (1995-02-01), Tao et al.
patent: 5424693 (1995-06-01), Lin
patent: 5525941 (1996-06-01), Roshen et al.
Giri Ajay P.
Knickerbocker John U.
Long David C.
Shinde Subhash L.
Studzinski Lisa M.
Blecker Ira D.
Collins D. M.
International Business Machines - Corporation
Picardat Kevin M.
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