Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-31
2001-08-28
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000
Reexamination Certificate
active
06281539
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to dense memory cells, and more particular to 6F
2
memory cells that include vertical metal oxide semiconductor field effect transistors (MOSFETS) and large deep trench (DT) capacitors. The present invention is also directed to a process of fabricating such a memory cell.
BACKGROUND OF THE INVENTION
Present trends in dynamic random access memory (DRAM) technology are constantly driven towards reduction in minimum feature size, F, and more compact cell layouts, i.e., denser than 8F
2
. As a result of the need for ever increasing array densities, the scalability of contemporary planar metal oxide semiconductor field effect transistor (MOSFET) cells for F=150 nm and smaller dimensions is facing fundamental concerns. The main concern with the scalability of the MOSFET cell is the increased P-well doping concentration needed to meet off-current objectives. It is well known in the art that increased array well doping concentration may result in a marked increase in array junction leakage, which degrades retention time. The problem of scalability related to the MOSFET cell, by itself, is driving the paradigm shift towards vertical MOSFET access transistors in the array.
A great depth of knowledge of, and experience with, deep trench (DT) storage capacitor technology exists. However, with increasingly smaller groundrules and denser cell layouts, the ability to obtain adequate DT storage capacitance (on the order of about 35fF) is being seriously challenged. The difficulty in obtaining adequate DT storage capacitance is due to several factors including: (1) limitations on the scalability of the thickness of the node dielectric; (2) limitations on the etch depth of the DT; and (3) reduction of capacitance area that occurs with groundrule reduction, e.g., scaling, and more dense cell layouts, i.e., 6F
2
and 7F
2
vs. 8F
2
. Reactive-ion etching (RIE) lag effect caused by smaller storage trench openings makes etching adequate deep trenches difficult. Filling of these extremely high aspect ratio (>50:1) trenches also presents major difficulties.
Furthermore, the high aspect ratios associated with aggressively scaled DT capacitors result in increased series resistance which, in turn, results in decreased signal development within a given time window. For a 6F
2
cell with a near 1×1 DT opening, it is expected that the above mentioned problems of capacitance and resistance may become a major problem by the 120 nm generation. For DRAM producers who have firmly established DT capacitor technology as the main stream storage element for longer than the past decade, it would be costly to switch to an alternative storage technology such as stacked capacitors with a high dielectric constant.
Thus there is a need for DRAM cells containing vertical access transistors, dense layouts (denser than about 8F
2
) and trench storage capacitors which yield sufficient capacitance and reduced series resistance to avoid degraded signal development.
Although some existing DRAM cells employing vertical MOSFETs offer very significant scalability advantages over conventional planar designs practiced today, there is still a great deal of room for improvement. For example, for cells using vertical MOSFETs and trench storage capacitors, a single bitline contact is commonly used to access a pair of bits; the pair of bits share a common silicon active area (AA). In this type of cell, dynamic coupling between the two back-to-back vertical MOSFETs results in charge pumping effects and loss of signal. Modeling has shown that electrons pumped into the P-well from a collapsing channel inversion layer of one cell may be collected by the storage node of the adjacent cell sharing the same AA. These coupling effects are accentuated as dimensions are scaled down. Modeling projections indicate that scalability to 100 nm and below may be problematic because of dynamic charge loss due to coupling between adjacent cells.
In addition to charge pumping problems, very dense prior art designs suffer from threshold voltage variations in the size of the silicon AA which occurs with overlay (alignment) errors between various masking levels and with dimensional variations of features formed by these masking levels.
Another problem faced with aggressively scaled DRAM cells is the increased aspect ratio (height to width) of the isolation regions. This is especially a concern with vertical MOSFETs in the array because of the requirement that the isolation trench be deep enough to cut the strap so as to prevent cell-to-cell leakage between straps. Typically, it is required that the isolation trench be at least 500 nm in depth to isolate the straps of the vertical MOSFETs. If the thickness of the pad layer is included, an isolation trench aspect ratio of 7:1 is anticipated by the 100 nm generation.
In view of the drawbacks mentioned hereinabove with prior art DRAM cell designs, there is a continued need to develop new and improved DRAM cell designs that are denser than prior art designs and have a larger DT size. A larger DT size is advantageous in dense DRAM cells since it provides a large storage capacitance and reduced series resistance to the array cell.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a dense DRAM cell (6F
2
) which is scalable to a minimum feature size of about 100 nm.
Another object of the present invention is to provide a dense DRAM cell wherein dynamic leakage due to adjacent cell activity is substantially eliminated.
A further object of the present invention is to provide a dense DRAM cell having a large deep trench (on the order of 2×1) size for large storage capacitance, reduced resistance and ease of fabrication.
A yet further object of the present invention is to provide a dense DRAM cell that contains an array trench isolation pattern (stripes 2F wide) that has reduced aspect ratio for simplified filling.
An additional object of the present invention is to provide a dense DRAM cell that utilizes silicon active areas whose dimension is independent of all overlay tolerances, thus greatly tightening the threshold voltage distribution.
An even further object of the present invention is to provide a fully self-aligned process of fabricating a dense DRAM cell which substantially eliminates sensitivity of AA size to all overlay variations.
These and other aspects and advantages are achieved in the present invention by utilizing storage trenches having a 2F×1F size and isolation stripes 2F wide to define an AA in combination with a vertical transistor.
In accordance with one aspect of the present invention, a 6F
2
memory cell is provided. Specifically, the 6F
2
memory cell of the present invention comprises:
a plurality of capacitors each located in a separate trench that is formed in a semiconductor substrate;
a plurality of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor is located above and electrically connected to a respective trench capacitor;
a plurality of dielectric-filled isolation trenches in a striped pattern about said transistors, said isolation trenches are spaced apart by a substantially uniform spacing;
a respective wordline electrically contacted to each respective gate conductor, said wordline is in the same direction as the isolation trenches; and
a bitline in contact with said bitline diffusion, wherein each bitline diffusion has a width that is defined by said spacing of said isolation trenches.
In accordance to the present invention, the active area of the transfer transistors is defined by the intersection of pairs of isolation trenches and pairs of trenches containing capacitors.
Another aspect of the present invention is directed to a process of fabricating the above-mentioned 6F
2
memory cell. Specifically, the process of the present invention comprises the steps of:
(a) providing a semiconductor substrate having a storage trench with a capacitor formed in said storage trench, said capacitor being vertically re
Divakaruni Rama
Mandelman Jack A.
Capella, Esq. Steven
International Business Machines - Corporation
Nguyen Cuong Q
Scully Scott Murphy & Presser
Thomas Tom
LandOfFree
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