Structure and method of vertical transistor DRAM cell having...

Details Structure and method of vertical transistor DRAM cell having... Structure and method of vertical transistor DRAM cell having...

2005-12-27

2005-12-27

Brock, II, Paul E. (Department: 2829)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S297000, C257S298000, C257S300000, C257S302000, C257S304000

Reexamination Certificate

active

06979851

ABSTRACT:
A structure and method is disclosed herein for a vertical transistor DRAM cell having a low leakage buried strap outdiffusion conductively connecting a storage capacitor in a lower portion of a trench to a vertical transistor thereabove. In the disclosed structure and method, the buried strap outdiffusion (BSOD) extends along a portion of the isolation collar having reduced thickness, the reduced thickness being substantially less than the thickness of the isolation collar otherwise. In a particular embodiment, a self-aligned lightly doped drain (LDD) extension is formed, extending between the BSOD and the vertical transistor above the LDD.

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