Structure and method of three dimensional hybrid orientation...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S255000, C257S347000, C257S206000, C257S278000, C257S330000, C257S369000, C257S401000, C257S622000, C257S628000

Reexamination Certificate

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10907622

ABSTRACT:
A method and device for increasing pFET performance without degradation of nFET performance. The method includes forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direction. In use, the device includes a nFET stack on a substrate using a first plane and direction, e.g., (100)<110> and a pFET stack on the substrate using a second plane and direction, e.g., (111)/<112>. An isolation region within the substrate is provided between the nFET stack and the pFET stack.

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