Structure and method of making a sub-micron MOS transistor

Details Structure and method of making a sub-micron MOS transistor Structure and method of making a sub-micron MOS transistor

2001-02-14

2003-10-14

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S197000, C438S299000, C438S301000, C257S344000, C257S408000, C257S411000, C257S346000, C257S336000

Reexamination Certificate

active

06632731

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to MOS Transistor and IC fabrication method, and specifically to the use of a nitride undercut to form a sub-micron MOS.
BACKGROUND OF THE INVENTION
The use of chemical etching to provide a controllable undercut has been used to produce conventional MOS transistors, which is known as a “T-gate” structure. A nitride undercut, using phosphoric acid, has been used specifically in the fabrication of triple implanted bipolar transistors, however, this process is not widely used now because of controllability issues required to manufacture ICs using current technology. The nitride undercutting process may remain a useful process in a certain application, such as in the manufacture of sub-micron MOS transistors.
Lightly doped (LDD) structures are widely used in state-of-the-art IC fabrication. The usual LDD process requires two implantation steps, however, one of the implantation steps is eliminated using the LDD method of the invention.
SUMMARY OF THE INVENTION
A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure
A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.
An object of the invention is to provide a method of fabrication for sub-micron transistors
Another object of the invention is to provide a simplified LDD process
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.


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Van Zant, Microchip Fabrication, 1997, McGraw-Hill, pp. 389, 394.*
Chatterjeeet al., Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process,International Electron Devices Meeting, Dec. 7 -10, 1997, pp 821-824.

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