Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2000-08-11
2001-09-11
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S189070, C365S168000
Reexamination Certificate
active
06288922
ABSTRACT:
BACKGROUND INFORMATION
1. Field of the Invention
The present invention relates to the field of integrated circuits, and particularly to a content addressable memory (CAM).
2. Description of Related Art
Networking companies are scrambling in a race to design and develop high performance network processing products for the terabit router market while reducing the cost to implement 10 giga-bits per second/OC192 and above optical carrier network interfaces. Terabit routers demand a fatter throughput of data packets for examining an incoming packet, retrieves a next hop location, and transfers the packet to destination. Among various designs and memory architectures, a ternary CAM is a popular choice due to its fast processing speed for parallel address matching and rule-based classification.
A ternary CAM cell is capable of storing information in three different logic states, a binary “0” state, a binary “1” state, and an “X” or “don't care” state. One characteristic of a CAM is that the entire chip is being accessed every cycle for a look-up, which consumes a large amount of power. Conversely, most other types of memories access only a specific address, which in turn consumes a relative small amount of power. But in a CAM, the entire chip has to be checked in parallel. Electrical power in a CAM is generally consumed from two sources, a set of compare lines and a set of match lines. Compare and matching lines are the ones that are actually switching in a CAM.
FIG. 1
illustrates a conventional ternary CAM cell
5
that employs a pair of data storage and comparator groups
11
and
12
and a conventional ternary CAM cell
10
that employs a pair of data storage and comparator groups
13
and
14
. If data is stored in data storage
15
, a compliment data is stored in data storage
19
. Transistors {overscore (A)}
16
, A
20
, B
17
, and {overscore (B)}
21
form an exclusive OR (XOR) function of {overscore (A)} B and A{overscore (B)}. In combination, the first pair of data storage and comparator groups
11
and
12
is used to code one bit. When data is to be stored, the data is sent to data storage
15
, and a complimentary data is being stored in data storage
19
.
During a compare operation, data storage and comparator group
11
is used for comparison with true comparand dataline C
0
18
, and data storage and comparator group
12
is used for comparison with the compliment value of the true comparand dataline {overscore (C
0
)}
22
. During a non-compare operation, comparand datalines C
0
18
and {overscore (C
0
)}
22
are both grounded to zero. For operation in a NMOS compare circuit, one of the comparand datalines C
0
18
or {overscore (C
0
)}
22
must be in a high-voltage state, while the other comparand dataline is in a low-voltage ,tate. The high-voltage dataline is the one that is activated for performing a compare operation. As a result, one-half of the datalines in the CAM cell region is toggled for each compare operation. Given the large amount of parallel compare operations in a CAM cell, the total electrical current consumed by comparand datalines represent a significant portion in a CAM.
Similar operations apply to data storage and comparator group
13
including a comparand dataline C
1
26
that couples to a transistor B
25
, a transistor {overscore (A)}, and a data storage
23
, and data storage and comparator group
14
including a comparand dataline {overscore (C
1
)}
30
that couples to a transistor {overscore (B)}
29
, a transistor A
28
, and a data storage
27
. The raw data is stored and the raw data is compared. A miss is detected if a match line
31
is pulled low through one of the four CAM cells.
FIG. 2
is a time diagram depicting conventional ternary CAM cell
10
with two datalines C
0
18
and C
1
26
, with corresponding compliments of comparand datalines {overscore (C
0
)}
22
and {overscore (C
1
)}
30
. For every cycle, both the comparand datalines C
0
or {overscore (C
0
)}, and C
1
or {overscore (C
1
)}, may switch up for evaluation and reset for precharge. As a result, there are four switching operations in two cycles, which consumes a significant amount of power from aCAM.
Accordingly, it is desirable to have a CAM circuit and method that reduces the number of switchings on a compare line, and thus effectively reducing the amount of power consumed.
SUMMARY OF THE INVENTION
The invention discloses a low-power ternary CAM by utilizing four encoded comparand datalines, C
0
, C
1
, C
2
, and C
3
in a twin ternary cell. The twin ternary cell is a composite of two ternary CAM bits. The two binary CAM bits are coded so that only one of the four comparand datalines is toggled during a compare operation. The encoded data is stored and used for comparison. In one embodiment, the four possible states for the 2-bit comparands are coded as 0001, 0010, 0100, and 1000.
Advantageously, the invention reduces power consumptions in a CAM by avoiding the storing and comparing of raw data. Moreover, the total number of switchings during a compare operation is significantly reduced, thereby resulting in a 50% or more power saving.
REFERENCES:
patent: 6081440 (2000-06-01), Washburn et al.
patent: 6101115 (2000-08-01), Ross
patent: 6108227 (2000-08-01), Voelkel
patent: 6137707 (2000-10-01), Srinivasan et al.
patent: 6169685 (2001-01-01), Gandini et al.
Kengeri Subramani
Wong Hing
Fernandez & Associates LLP
Hoang Huan
Silicon Access Networks, Inc.
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