Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-03-22
2005-03-22
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06871332
ABSTRACT:
Manipulation of a multi-wide object class design layout to facilitate design rule checking or automatic correction of design rule errors is improved by deriving wide class objects from geometries of the design layout, and applying certain rules to non-virtual boundaries of the wide class objects that are not applied to virtual boundaries of the wide class objects. In an exemplary embodiment, the wide class objects are preferably derived by sizing down, then sizing up, each geometry by a sizing factor equal to half the minimum width of the particular wide class object less an amount that preferably corresponds to that represented by a minimum resolution of the design layout. Portions of a geometry that are otherwise excluded as being too narrow in width, but that lie wholly within a correction factor of the boundary of the wide class object otherwise derived, are preferably included to form effective wide class objects.
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Li Mu-Jing
Yang Amy
Bowers Brandon
Garbowski Leigh M.
Sun Microsystems Inc.
Zagorin O'Brien Graham LLP
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