Structure and method for SDRAM dynamic self refresh entry and ex

Details Structure and method for SDRAM dynamic self refresh entry and ex Structure and method for SDRAM dynamic self refresh entry and ex

1996-10-18

1998-08-11

Beausoliel, Jr., Robert W.

Excavating

39518318, G01R 3128

Patent

active

057937761

ABSTRACT:
JTAG test logic and a memory controller place an SDRAM in a self refresh mode prior to beginning JTAG testing. The memory controller can complete a current memory access and otherwise prepare for the JTAG test. During the JTAG test, self refresh mode operation of the SDRAM retains data without the need for a clock signal or refresh signals which are suspended for the JTAG test. Accordingly, after the JTAG test, circuit operation can continue without reinitializing data in the SDRAM.

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