Structure and method for parallel testing of dies on a...

Details Structure and method for parallel testing of dies on a... Structure and method for parallel testing of dies on a...

2006-12-21

2008-11-11

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

Reexamination Certificate

active

07449350

ABSTRACT:
In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

REFERENCES:
patent: 5366906 (1994-11-01), Wojnarowski et al.
patent: 7122829 (2006-10-01), Lunde

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