Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2006-07-11
2006-07-11
Chace, Christian P. (Department: 2189)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S310000, C711S113000, C711S173000
Reexamination Certificate
active
07076579
ABSTRACT:
A structure and a method of managing multiple sections of a buffer provide an initial block register and a memory unit. A buffer managing unit is capable of operating consecutively in a specific section set between the initial block register and the end block register. When the pickup head leaves the original track and skips to another track to read data, the initial block register and the end block register are reset. The contents in the original register are stored in one division of the memory unit. In this way, the original data stored in the specific section is not abandoned. When the pickup head needs to read the data in the original track, the contents in the registers are restored from the division of the memory unit to the registers.
REFERENCES:
patent: 5727232 (1998-03-01), Iida et al.
patent: 5778420 (1998-07-01), Shitara et al.
Chace Christian P.
Hsu Winston
Lite-On It Corporation
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