Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-06-23
1998-07-21
Niebling, John
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438595, H01L 213205, H01L 214763
Patent
active
057834792
ABSTRACT:
A structure and method for manufacturing improved FETs having T-shaped gates can reduce the parasitic resistance of the gate and source/drain of an FET. In the improved FETs having T-shaped gates formed according to the invention, since a buffer layer under spacers comprises a gate oxide layer and a thicker first dielectric layer, there is no stress problem as in the prior art. Furthermore, since the polysilicon gate is lower in height than the spacers, a bridge effect can be prevented. Meanwhile, since a T-shaped conductive layer is formed to increase the equivalent width of the gate, thereby avoiding the narrow line-width effect.
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Huang Tiao-Yuan
Lin Horng-Chih
Booth Richard A.
National Science Council
Niebling John
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