Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-10-18
2005-10-18
Lebentritt, Michael (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S372000, C257S347000
Reexamination Certificate
active
06956266
ABSTRACT:
A method and structure for an integrated circuit comprising a substrate of a first polarity; a trench structure in the substrate; a well region of a second polarity abutting the trench structure; and a heavily doped region of the second polarity abutting the trench structure, wherein the heavily doped region is adapted to suppress latch-up in the integrated circuit, wherein the heavily doped region comprises a sub-collector region, and wherein the trench structure comprises a deep trench structure or a trench isolation structure. The integrated circuit further comprises a p+ anode in the well region and a n+ cathode in the well region, wherein the integrated circuit is configured as a latchup robust p-n diode. In another embodiment, the integrated circuit further comprises a p+ anode in the well region; a n+ cathode in the well region; and a gate structure over the p+ anode and n+ cathode.
REFERENCES:
patent: 4486266 (1984-12-01), Yamaguchi
patent: 4578128 (1986-03-01), Mundt et al.
patent: 4656730 (1987-04-01), Lynch et al.
patent: 4729006 (1988-03-01), Dally et al.
patent: 4862233 (1989-08-01), Matsushita et al.
patent: 4881105 (1989-11-01), Davari et al.
patent: 4926233 (1990-05-01), Hutter
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5029321 (1991-07-01), Kimura
patent: 5067002 (1991-11-01), Zdebel et al.
patent: 5086010 (1992-02-01), Kimura
patent: 5122846 (1992-06-01), Haken
patent: 5554862 (1996-09-01), Omura et al.
patent: 5612242 (1997-03-01), Hsu
patent: 5780353 (1998-07-01), Omid-Zohoor
patent: 6011283 (2000-01-01), Lee et al.
patent: 6190954 (2001-02-01), Lee et al.
patent: 6514833 (2003-02-01), Ishida et al.
patent: 6518628 (2003-02-01), Krautschneider et al.
patent: 6525394 (2003-02-01), Kuhn et al.
patent: 6600199 (2003-07-01), Johnson et al.
patent: 2002/0135024 (2002-09-01), Logan et al.
patent: 2003/0205765 (2003-11-01), Masuoka
patent: 63-304661 (1988-12-01), None
Voldman et al., “Retention Time and Soft Error Rate Improvement by Tailoring Well Doping in Trench Dram Cells”, IBM Technical Disclosure Bulletin, vol. 33, No. 1B, 1990, pp. 35-36.
L.A. Nesbit, Method of Forming Shallow Trench Isolation With Selectively Doped Sidewalls, vol. 31 No. 2, 1988, pp. 418-420.
Voldman Steven H.
Watson Anne E.
Canale Anthony
Lebentritt Michael
Lindsay Jr. Walter L.
McGinn & Gibb PLLC
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