Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-03
2002-08-20
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000, C257S328000
Reexamination Certificate
active
06437401
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to device and device fabrication and, more particularly, to transistor-trench capacitor memory cells.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) employ capacitors for the storage of charge. The presence or absence of stored charge, its charge storage state, defines information contained within capacitors in ICs. For example, memory devices, including random access memories (RAMs), such as dynamic RAMs (DRAMs), store charge in capacitors; the relative quantity of charge in the capacitor is commonly used to represent a bit of data (“0” or “1”).
A DRAM IC includes an array of memory cells interconnected by rows and columns of conductive lines. The rows and columns of conductive lines are typically referred to as wordlines and bitlines, respectively. Cells in the memory array may be randomly accessed, for reading or writing bits of data, by activating appropriate wordlines and bitlines.
A DRAM memory cell typically includes an access transistor that is connected serially with a storage capacitor. Typically, the access transistor of a DRAM memory cell consists of a metal-oxide-semiconductor field effect transistor (MOSFET). The MOSFET includes a semiconductor body (substrate) of a first conductivity type and first and second regions of the opposite conductivity type which are separated by a portion of the substrate which is covered by a gate conductor that is separated from the surface of the substrate by a dielectric layer. The first and second regions are referred to as bitline and storage node diffusion (also commonly referred to as the buried-strap outdiffusion) regions or first and second input/output region, and comprise the drain and source regions of the MOSFET. The diffusion region which serves as the drain or source depends upon the operation of the transistor within the memory cell (i.e., write “1”, write “0”, read “1”, read “0”, data refresh). For each memory cell, the gate of the MOSFET is connected to a wordline conductor, the bitline diffusion is connected to the bitline conductor, and the storage node diffusion is connected to the storage capacitor. Application of a voltage to the wordline (active state) switches MOSFETs connected to that wordline to the on-state (conductive), allowing the exchange of charge between the bitline and the storage capacitor. When the MOSFET is in the on-state memory cell operations such as write “1”, write “0”, read “1”, read “0”, and data refresh may be performed. MOSFETs connected to wordlines which are inactive are in the off-state (non-conductive). In the off-state the MOSFET isolates the storage capacitor from the bitline. This allows charge stored in the capacitor, which represents a stored logic “1” or “0”, to be retained for a useful period of time.
Trench capacitors are commonly used as storage elements in DRAMs. A trench capacitor is a three-dimensional structure formed into a semiconductor substrate. A conventional trench capacitor comprises a trench etched into a silicon substrate. The trench is typically lined with an insulating material that serves as the dielectric of the storage capacitor. A first electrode of the storage capacitor consists of a conductive material, typically n+ type doped polysilicon, which fills a portion of the trench. The first electrode is typically referred to as the capacitor node. A second electrode of the storage capacitor, the capacitor plate (or counter-electrode), is formed by a diffused region adjacent a lower portion of the trench sidewall. The diffused plate electrode (also commonly referred to as the buried-plate diffusion) is typically formed by outdiffusing n+ type dopant, from a dopant source within the trench, into the p-type doped substrate surrounding a lower portion of the trench, and is commonly referred to as the buried-plate electrode. To assure an adequate time of retention of data (“0” or “1”) stored in the capacitor when the MOSFET of the memory cell is in the off-state, leakage current to and from the capacitor node must typically be less than 1fA/cell.
FIG. 1
shows a prior art vertical MOSFET-trench capacitor DRAM cell including a vertical access MOSFET having a gate conductor
32
, a bitline diffusion (a first input/output region)
25
, and a storage node diffusion (a second input/output region)
22
formed in a semiconductor body (substrate)
20
having a top surface
13
. The vertical MOSFET overlies a storage capacitor within the trench. Storage node diffusion
22
is electrically connected to a storage capacitor consisting of a storage capacitor node electrode
17
(typically of n+ type doped polysilicon), a capacitor dielectric
15
layer (typically a silicon nitride/silicon oxide sandwich), and a buried-plate diffusion electrode
12
(typically an n+ type doped pocket in a p-type doped region of a monocrystalline silicon substrate). A junction between the p-type doped substrate region (also referred to as the array p-well)
20
and a band of n-type dopant
14
is denoted by
28
. The band of n-type dopant
14
serves to isolate the p-type doped substrate region of the cell from other circuit elements on the chip. Leakage of charge to and from storage capacitor node electrode
17
may result from a variety of mechanisms. Sub-threshold conduction between bitline diffusion
25
and storage node diffusion
22
of the MOSFET, storage node diffusion
22
leakage to substrate
20
, and parasitic MOSFET action between storage node diffusion
22
and buried-plate diffusion electrode
12
are mechanisms that typically contribute to leakage resulting in loss of stored data. Sub-threshold leakage may be limited by appropriate choice of threshold voltage of the MOSFET. Storage node diffusion
22
to substrate
20
leakage may be controlled by methods such as limiting the maximum substrate doping concentration adjacent to storage node diffusion
22
and appropriate anneal conditions during fabrication. However, as the dimensions of the DRAM cell are scaled down, control of the parasitic MOSFET action between storage node diffusion
22
and buried-plate diffusion electrode
12
becomes increasingly problematic.
To limit parasitic MOSFET leakage between storage node diffusion
22
and buried-plate diffusion electrode
12
to an acceptable level, an isolation collar
16
, typically of silicon oxide, is provided therein on a sidewall of the trench between storage node diffusion
22
and buried-plate diffusion electrode
12
. The parasitic MOSFET comprises source/drain diffusions consisting of storage node diffusion
22
and buried-plate diffusion
12
, with the gate conductor of the parasitic MOSFET being storage capacitor node electrode
17
. Isolation collar
16
is the equivalent gate dielectric of the parasitic MOSFET. By increasing the thickness of the isolation collar
16
, the threshold voltage of the parasitic MOSFET may be increased, reducing its off-state leakage current. Typically, an isolation collar thickness of between approximately 25-70 nm is required to reduce the parasitic leakage current to 1fA/cell or less.
Continued demand for DRAM with ever increasing density of bits/chip requires that the design groundrules be aggressively reduced. For example, design rules have been scaled from 0.25 microns (&mgr;m) down to below 0.12 &mgr;m. The shortest dimension for the opening of the storage trench is typically approximately equal to the design rule. At a design rule of 0.25 &mgr;m there is ample room within the trench to form an isolation collar
16
as thick as 70 nm and still fill the trench with storage node capacitor electrode material
17
. However, as design rules are reduced below 0.12 &mgr;m, processing of a trench capacitor having an isolation collar sufficiently thick to reduce the parasitic MOSFET leakage current to 1A/cell or less becomes increasingly difficult. Smaller trench openings necessitate a corresponding reduction in isolation collar thickness to facilitate filling of the trench with storage node capacitor electrode material
17
. However, to reduce the parasitic l
Knorr Andreas
Kudelka Stephan
Mandelman Jack A.
Rahn Stephen
Tews Helmut
Infineon - Technologies AG
Meier Stephen D.
Ostroff Irwin
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