Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-12-29
2001-05-08
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06228765
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the manufacture of interconnections within integrated circuits. In particular, it relates to the manufacture of interconnection formed in cavities etched into a previously formed dielectric layer, often known as a “damascene” process.
BACKGROUND OF THE INVENTION
In known damascene type interconnect formation processes, a pattern of cavities is formed in a dielectric layer to correspond to the required pattern of later formed interconnect wirings and contacts. A metal or other conductive material is deposited over the entire surface of the wafer, to sufficient depth to fill all the cavities in the dielectric layer. A mechanical or chemical-mechanical polishing step is then applied to the wafer to remove the conductive material other than that situated within the cavities. Such polishing is the only way to ensure an almost perfectly planar upper surfaces, with the wirings and contacts being flush with the upper surface of the dielectric.
However, the polishing for the removal of such metal is undesirable because a long time is needed to remove a thick metal layer, thus increasing the total processing time required to produce an integrated circuit.
An object of the present invention is to provide a method for forming damascene type wirings and contacts in integrated circuits where the requirement for the polishing of conductive material is reduced or eliminated.
Another object of the present invention is to provide a novel process for forming contacts and interconnect wirings in integrated circuits.
Another object of the present invention is to provide such a process which easily yields contacts and wirings having upper surfaces which are substantially coplanar with surrounding dielectric layers.
SUMMARY OF THE INVENTION
According to principles of the present invention, a method is provided for forming conductive members in an integrated circuit comprising the steps of:
a) providing an underlying layer, having an upper surface;
b) depositing a first dielectric layer on the upper surface of the underlying layer;
c) forming cavities extending at least partially through the first dielectric layer in locations selected for the formation of the conductive members; and
d) filling the cavities with a conductive material.
The method includes, between steps (b) and (c), the steps of:
e) depositing a first conductive layer on an upper surface of the first dielectric layer; and
f) depositing a second dielectric layer on the first conductive layer, and step (d) includes the steps of:
g) forming a second conductive layer on all internal surfaces of the cavities; and
h) electrolytically depositing a further conductive material over the second conductive layer.
According to an embodiment of the present invention, the further conductive material is deposited to a thickness sufficient to substantially fill the cavities.
According to an embodiment of the present invention, step (g) comprises the steps of depositing a second conductive layer over all exposed surfaces of the structure; and removing the second conductive layer from all surfaces of the structure other than the internal surfaces of the cavities.
According to an embodiment of the present invention, the second conductive layer is removed by a polishing process step.
According to an embodiment of the present invention, the method includes, after step (d), the step of polishing the upper surface of the structure to remove excess conductive material protruding above an upper surface of the second dielectric layer.
According to an embodiment of the present invention, the method includes, after step (d), the step of polishing the upper surface of the structure to remove conductive material protruding above the upper surface of the first dielectric layer, and to entirely remove the second dielectric layer and the first conductive layer.
According to an embodiment of the present invention, the underlying layer is a conductive or semiconductive layer, and the cavities extend completely through the first dielectric layer, whereby the resulting conductive member is in contact with the underlying conductive or semiconductive layer.
According to an embodiment of the present invention, the cavities extend only partially through the first dielectric layer, the resulting conductive member being electrically isolated from the underlying layer.
According to an embodiment of the present invention, the underlying layer is a dielectric layer including contact members extending vertically therethrough, the cavities extending completely through the first dielectric layer, whereby the resulting conductive members are interconnect wirings, electrically in contact with the underlying contact members.
Certain embodiments of the current invention will be described, by way of example, with reference to the accompanying diagrams:
REFERENCES:
patent: 5098860 (1992-03-01), Chakravorty et al.
patent: 5474651 (1995-12-01), Huebner
patent: 01 144 752 (1985-06-01), None
Morand Yves
Moussavi Mehdi
Galanthay Theodore E.
Iannucci Robert
Lee Calvin
Seed IP Law Group
Smith Matthew
LandOfFree
Structure and method for forming conductive members in an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Structure and method for forming conductive members in an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structure and method for forming conductive members in an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2507139