Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-11-08
2004-04-27
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S445000, C438S692000, C438S694000, C438S695000, C438S696000, C438S697000, C438S510000, C438S506000, C438S701000, C438S713000, C438S736000
Reexamination Certificate
active
06727158
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to semiconductor devices, and more particularly to a structure and method for forming a trench, contact hole, or via, and subsequently depositing a material therein, that is less susceptible to the formation of voids.
BACKGROUND OF THE INVENTION
One type of structure that is commonly found in semiconductor devices is an isolation region, which is used to isolate or prevent current flow between adjacent active regions formed in a semiconductor substrate. Active regions are generally doped regions implanted in a substrate. For example, source/drain regions of a transistor can be considered active regions. An isolation region is formed between the source/drain regions of adjacent transistors to prevent current from flowing from one transistor to the other. This type of isolation region can be found in many conventional memory devices.
One method of forming isolation regions uses a process of the local oxidation of silicon (LOCOS). Typically, a nitride layer is formed on a substrate and subsequently patterned and etched to expose portions of the substrate surface where the isolation regions are to be formed. Thermal oxide is then grown in the exposed areas to form oxide isolation regions. The nitride layer is then removed, and the substrate is ready for device formation in the areas defined by the isolating regions of oxide. This process is well known and will not be described in any greater detail herein. It is enough to note that a shortcoming associated with the LOCOS process is the formation of “bird's beak” spurs that consume lateral area on the surface of a substrate. However, where high density integration of the active regions is desired, sacrificing surface area to accommodate the bird's beak spurs of an isolation region is unacceptable.
An alternative process that does not have the problems associated with LOCOS isolation regions is forming trench-type isolation regions. In this process, rather than performing local oxidation, a trench is formed, and insulating material is deposited therein to form the isolation region. As a result of forming the isolation region by depositing the insulating material into a trench, rather than growing a thermal oxide, the lateral dimensions of the isolation region can be controlled to a much greater degree. Moreover, the formation of bird's beak spurs is no longer an issue since the profile of the trench determines the profile of the isolation region. The conventional process for forming a shallow trench isolation region is generally illustrated by FIG.
1
.
The process begins with masking and etching a trench
136
through a silicon nitride layer
106
, a pad oxide layer
104
, and into a substrate
102
(
FIGS. 1
a
and
1
b
). As illustrated in
FIG. 1
b
, the opening of the trench
136
has a dimension d
1
. An layer of insulating material
140
is formed in the trench and over the silicon nitride layer
106
(
FIG. 1
c
). An etch process is then performed to etch back the layer of insulating material
140
and the silicon nitride layer
106
, leaving the pad oxide layer
104
and an isolation region
142
(
FIG. 1
d
). The pad oxide layer
104
is then removed.
As the dimension d
1
is reduced to accommodate the smaller feature sizes of current devices, forming material in the trench
136
becomes more difficult because of step coverage issues. As illustrated in
FIG. 1
c′
, a void
150
may be formed in the layer of insulating material
140
because of step coverage effects at the opening of the trench
136
. As is acknowledged in the art, the creation of voids during the fabrication of semiconductor devices compromise the structure and ultimately the reliability of the devices.
FIGS. 1
d′
and
1
e′
illustrate the structure resulting from the conventional process where the void
150
is formed during the formation of the layer of insulating material
140
. As previously mentioned, the creation of voids during device fabrication is highly undesirable. Therefore, there is a need for an alternative method for forming an isolation structure that is less susceptible to the formation of voids.
SUMMARY OF THE INVENTION
The present invention is directed to a structure and method for filling an opening in a semiconductor structure that is less susceptible to the formation of voids. A first layer of a first material is formed over the layer in which the opening is to be formed, and a faceted opening is formed in the first layer. The opening in the underlying layer is subsequently formed, and the material that is to fill the opening is deposited over the faceted opening and into the opening of the underlying layer. The faceted opening in the first layer can be formed by performing an isotropic etch on the first layer through an opening in a mask layer that is formed over the first layer.
REFERENCES:
patent: 4639288 (1987-01-01), Price et al.
patent: 6159823 (2000-12-01), Song et al.
patent: 6177331 (2001-01-01), Koga
patent: 6372602 (2002-04-01), Mitsuiki
patent: 6548371 (2003-04-01), Fujimaki
Scott Clark, “Chemical Etching of Silicon Nitride (Si3N4) with Hot Phosphoric Acid (H3PO4),” Bold Technologies Technical Paper (2000), pp. 1-6.*
Nathan Cheung, Lecture notes (handout) EE 143, Lecture 15, University of California Berkeley (2000).
Bossler Mark A.
Inman Chris L.
Polinsky William A.
Sundt Dirk J.
Videla Gabriel G.
Dorsey & Whitney LLP
Loke Steven
Magee Thomas
Micro)n Technology, Inc.
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