Structure and method for a two-bit memory cell

Details Structure and method for a two-bit memory cell Structure and method for a two-bit memory cell

2005-03-01

2005-03-01

Dang, Phuc T. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S401000

Reexamination Certificate

active

06861696

ABSTRACT:
According to one exemplary embodiment, a two-bit memory cell situated over a substrate comprises a tunnel oxide layer situated over the substrate. The two-bit memory cell further comprises a first spacer and a second spacer situated over the tunnel oxide layer, where the first spacer is a first data bit storage location in the two-bit memory cell and the second spacer is a second data bit storage location in the two-bit memory cell. The first spacer and the second spacer may be, for example, silicon nitride or polycrystalline silicon. According to this exemplary embodiment, the two-bit memory cell further comprises an oxide layer situated between the first spacer and the second spacer. The two-bit memory cell further comprises a control gate situated over the oxide layer.

REFERENCES:
patent: 5108939 (1992-04-01), Manley et al.
patent: 6153904 (2000-11-01), Yang
patent: 6329687 (2001-12-01), Sobek et al.

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