Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
1999-01-28
2001-07-24
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S309000, C438S312000, C438S321000, C438S322000, C257S511000, C257S513000
Reexamination Certificate
active
06265276
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a structure and fabrication process of a semiconductor device, and more specifically to a high performance complementary bipolar transistor.
BACKGROUND OF THE INVENTION
A complementary bipolar transistor device is attracting much attention as a device implementing an ultra high speed, low power consumption LSI (large scale integrated circuit). One conventional example is disclosed in “An NPN 30 GHz, PNP 32 GHz fT Complementary Bipolar Technology”, Onai, et al. 1993 IEEE. In such a complementary bipolar device, the performance of the device is determined by the poorer of NPN and PNP transistors which is poorer in characteristic. It is, therefore, desirable to match the characteristics of both transistors with each other, and in the conventional example, the NPN and PNP transistors are arranged in a completely symmetrical configuration. However, the conventional device requires a step of separately forming a base polysilicon electrode and an emitter polysilicon electrode by ion implantation or the like. The conventional design is disadvantageous in the number of fabrication steps, TAT (Turn Around Time) and cost.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to reduce the number of required fabricating steps for a transistor device such as a complementary bipolar transistor device.
It is another object of the present invention to provide a process for fabricating a transistor device such as the complementary bipolar transistor device capable of operating at high speeds.
It is still another object of the present invention to provide a structure of a transistor device, such as the complementary bipolar transistor device, which can operate at high speeds and has a high fT (high cut off frequency).
A semiconductor device according to one aspect of the present invention includes at least first and second electrically conductive films which are electrically separated from each other; a first transistor using the first conductive film as a base electrode, and the second conductive film as an emitter electrode; and a second transistor using the first conductive film as an emitter electrode, and the second conductive film as a base electrode.
A semiconductor device according to another aspect of the present invention includes at least first and second electric conductive films which are electrically separated from each other; a first transistor having a portion of the second conductive film formed in an opening opened in the first conductive film; and a second transistor which includes a portion of the second conductive film located outside a portion of the first conductive film.
A semiconductor device according to still another aspect of the present invention includes at least first and second electric conductive films which are electrically separated from each other; a first transistor comprising a base electrode formed by the first conductive film, and an emitter electrode formed, by the second conductive film, in an opening formed in the base electrode; and a second transistor includes an emitter electrode formed by the first conductive film, and a base electrode formed, by the second conductive film, outside the emitter electrode of the second transistor.
According to another aspect of the present invention, a process wherein a step of forming a first insulating film on a semiconductor substrate, a step of forming a first opening in the first insulating film, a step of forming a first conductive film; a step of forming a second insulating film, a step of-combining the second insulating film and the first conductive film to form a multi-layer film, a step of forming a second opening in a part of the multi-layer film, a step of forming a third insulating film on a side wall of the multi-level film structure of the second insulating film and the first conductive film, and on a side wall of the second opening, and a step of forming a second conductive film.
According to another aspect of the present invention, a process for fabricating a semiconductor device, includes a step of forming a first insulating film on a semiconductor substrate, a step of forming a first opening in the first insulating film, a step of forming a first conductive film, a step of forming a second insulating film, a step of combining the second insulating film and the first conductive film to form a multi-layer film, a step of forming a second opening in a part of the multi-layer structure of the second insulating film and the first conductive film, a step of forming a third insulating film on a side wall of the multi-level film structure of the second insulating film and the first conductive film, and on a side wall of the second opening, a step of forming a second conductive film, a step of forming a diffusion layer of a first conductivity type by using the first conductive film as a diffusion source, and a step of forming a diffusion layer of a second conductivity type by using the second conductive film as a diffusion source.
In the present invention, it is possible to form the base electrode of an NPN transistor and the emitter electrode of a PNP transistor from a single conductive film, and to form the emitter electrode of the same NPN transistor and the base electrode of the same PNP transistor from another single conductive film. Both single conductive films are layer upon one another so as to share a common semiconductor substrate. Therefore, the present invention can eliminate the necessity of a step for individually forming the separate base and emitter electrodes. Thus, the present invention can prevent an increase of the number of required fabrication steps, reduce TAT (Turn Around Time—a time required to supply products from a semiconductor maker to users), and to reduce the cost of the device. Moreover, the present invention makes it possible to achieve an isolation between the emitter and base both in the NPN and PNP transistors, for example, with the same dielectric side wall in a self alignment structure, so that further miniaturization is possible.
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“An NPN 30 GHz, PNP 32 GHz fT Complementary Bipolar Technology”, Onai, et al. (IEEE, International Electron Devices Meeting Technical Digest, p. 63-66; Dec. 1993).
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Dang Trung
Kebede Brook
Sonnenschein Nath & Rosenthal
Sony Corporation
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