Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2002-05-24
2003-09-02
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S455000, C438S459000
Reexamination Certificate
active
06613643
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to improved Silicon-on-Insulator structures. More particularly, the present invention relates to methods for removing heat from Silicon-on-Insulator devices and devices having such characteristics.
BACKGROUND ART
Silicon-on-Insulator (SOI) technology is of growing importance in the field of integrated circuits. SOI technology involves forming transistors in a relatively thin layer of semiconductor material overlying a layer of insulating material. More particularly, SOI technology is characterized by the formation of a thin silicon layer (device region) for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources and drains are formed, for example, by implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor layer structure.
Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). Devices, such as metal oxide silicon field effect transistors (MOSFET), have a number of advantages when formed on SOI wafers versus bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N
+
to P
+
spacing and hence higher packing density due to ease of isolation; absence of latch-up; lower voltage applications; and higher “soft error” upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Although there are significant advantages associated with SOI technology, there are significant disadvantages as well. For example, poor heat removal from devices on an SOI substrate is a significant disadvantage. Electrical devices generate heat, and the inability to remove or dissipate the heat results in poor and/or inconsistent performance of the electrical devices, or even in some instances device and/or substrate degradation.
There is poor heat removal for devices on SOI substrates primarily because of the oxide insulation layer. More specifically, the oxide insulation layer has a markedly lower thermal conductivity than the thermal conductivity of conventional bulk silicon (typically used as semiconductor substrates), which typically surrounds semiconductor devices. For example, the thermal conductivity of silicon dioxide is about 1.4 W/m°C. while the thermal conductivity of conventional bulk silicon is about 150 W/m°C. As a result, the buried oxide layer undesirably insulates thermally the device region in SOI substrates.
In view of the aforementioned disadvantages, there is a need for SOI devices of improved quality, particularly SOI devices having improved heat removal characteristics, and more efficient methods of making such SOI devices.
SUMMARY OF THE INVENTION
As a result of the present invention, an SOI substrate having improved heat removal characteristics (from the device layer) is provided. By forming an SOI substrate according to the present invention, improved performance of devices subsequently formed on the SOI substrate is facilitated. Moreover, forming an SOI substrate in accordance with the present invention does not degrade or deleteriously effect the advantageous properties and characteristics commonly associated with SOI technology (improved speed performance at higher-operating frequencies, higher packing density, absence of latch-up, lower voltage applications, and higher “soft error” upset immunity).
In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate, involving the steps of providing a first silicon substrate and a second silicon substrate; surface modifying at least one of the first silicon substrate and the second silicon substrate by forming a pattern thereon; forming a first insulation layer over the first silicon substrate to provide a first structure and a second insulation layer over the second silicon substrate to provide a second structure; bonding the first structure and the second structure together so that the first insulation layer is adjacent the second insulation layer; and removing a portion of the first or second silicon substrate thereby providing the silicon-on-insulator substrate.
In another embodiment, the present invention relates to a method of facilitating heat removal from a device layer of a silicon-on-insulator substrate formed by a bond and etch-back process, the silicon-on-insulator substrate comprising bulk silicon, a buried insulation layer over the bulk silicon, and a silicon device layer over the insulation layer, involving the step of removing from about 500 Å to about 4,000 Å in thickness of silicon from a portion of the bulk silicon thereby forming a patterned surface in the bulk silicon, the patterned surface in the bulk silicon adjacent the buried insulation layer.
In yet another embodiment, the present invention relates to a silicon-on-insulator substrate, containing a silicon substrate layer having a patterned top surface; an insulation layer over the patterned top surface of the silicon substrate layer, the insulation layer having a first thickness over patterned portions of the silicon substrate layer and a second thickness over unpatterned portions of the silicon substrate layer; and a silicon device layer comprising silicon over the insulation layer.
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Buynoski Matthew S.
Krishnan Srinath
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Thomas Toniae M.
Zarabian Amir
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