Structurally-enhanced integrated circuit package and method...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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Details

C257S693000, C257S773000, C257S780000, C257S783000, C257S787000, C257SE23021, C257SE23069, C438S612000, C438S613000, C438S614000

Reexamination Certificate

active

07830006

ABSTRACT:
A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free from encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.

REFERENCES:
patent: 6114187 (2000-09-01), Hayes
patent: 7253520 (2007-08-01), Yoshida et al.
patent: 7271491 (2007-09-01), Akram
patent: 7358618 (2008-04-01), Shibata
patent: 7514786 (2009-04-01), Hsu
patent: 7545036 (2009-06-01), Terui et al.
patent: 2002/0027257 (2002-03-01), Kinsman et al.
patent: 2002/0195720 (2002-12-01), Miyazaki
patent: 2003/0235976 (2003-12-01), Zakel et al.

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