Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-10-25
2010-06-01
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S149000, C711SE12088
Reexamination Certificate
active
07730276
ABSTRACT:
A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.
REFERENCES:
patent: 4414624 (1983-11-01), Summer et al.
patent: 5166927 (1992-11-01), Lida et al.
patent: 5179557 (1993-01-01), Kudo
patent: 5390184 (1995-02-01), Morris
patent: 5469003 (1995-11-01), Kean
patent: 5606562 (1997-02-01), Landguth
patent: 5610914 (1997-03-01), Yamada
patent: 5841771 (1998-11-01), Irwin et al.
patent: 5953336 (1999-09-01), Moore et al.
patent: 6160813 (2000-12-01), Banks et al.
patent: 6480911 (2002-11-01), Lu
patent: 6546017 (2003-04-01), Khaunte
patent: 6588017 (2003-07-01), Calderone
Nikologiannis, A.; Katevenis, M.,“Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques”; Communications, 2001. ICC 2001. IEEE International Conference onvol. 7, Jun. 11-14, 2001 pp. 2048-2052 vol. 7 Digital Object Identifier 10.1109/ICC.2001.937019.
Sundar Iyer, Amr Awadallah, Nick McKeown, “Analysis of a packet switch with memories running slower than the line-rate,” Stanford university computer system laboratory, May 2000., 1-47 pgs.
Amit Prakash, Sadia Sharif, Adnan Aziz, “An O(log2N) parallel algorithm for out put queuing,” University of Texas at Austin, 2002, 0-7803-7476-2/02 2002 IEEE, 7 pgs.
Biplab Sikdar et al.,“An Integrated Model for the Latency and Steady-State Throughtput of TCP Connections”, Dept of Electrical, Computer and Science Engineering, Rensselaer Polytechnic Institute, Performance Evaluation, vol. 46, No. 2-3 pp. 139-154, Oct. 2001. (Abstract).
Mutlu Arpaci, John Copeland, “Buffer Management for Shared Memory ATM Switches”, IEEE Communication Surveys, http://www.comsoc.org/pubs/surveys, First Quarter 2000, 1-10 pgs.
Andreas Frey, Yoshita Takahashi, “A note on an M/G1/1/N queue with vacation time and exhaustive service discipline,” NTT Multimedia Network Laboratories.
Manjunath, D.; Sikdar, B.;“Variable Length Packet Switches: Delay, Analysis of Crossbar Switches under Poisson and Self Similar Traffic”,INFOCOM 2000. 19th Annual Joint Conference of the IEEE Computer and Communications Societies. Proceedings. IEEEvol. 2, Mar. 26-30, 2000 pp. 1055-1064 vol. 2 Digital Object Identifier 10.1109/INFCOM.2000.832281.
U.S. Appl. No. 11/258,685, filed Oct. 25, 2005, Kavipurapu, G. N. et al., entitled “Scalable Shared Network Memory Switch for an FPGA”, 25 pgs., Xilinx, Inc. 2100 Logic Drive, San Jose, California, 95124.
U.S. Appl. No. 11/259,394, filed Oct. 25, 2005, Kavipurapu, G. N. et al., entitled “Time Based Data Storage for Shared Network Memory Switch”, 23 pgs., Xilinx, Inc. 2100 Logic Drive, San Jose, California, 95124.
U.S. Appl. No. 11/258,682, filed Oct. 25, 2005, Kavipurapu, G. N. et al., entitled “Class Queue for Network Data Switch to Identify Data Memory Locations by Arrival Time”, 23 pgs., Xilinx, Inc. 2100 Logic Drive, San Jose, California, 95124.
Massiglia, Paul, The RAID Book, RAID Advisory Board, 6th Edition, Chapter 4: Disk Striping and Mirroring, Feb. 1997, pp. 84-85.
Althouse Chris
Kavipurapu Gautam Nag
Rao Sweatha
Bragdon Reginald G
Lo Kenneth M
Maunu LeRoy D.
Ward Thomas A.
XILINX Inc.
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