Striping across multiple cache lines to prevent false sharing

Details Striping across multiple cache lines to prevent false sharing Striping across multiple cache lines to prevent false sharing

2007-02-27

2007-02-27

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S130000, C711S154000, C711S157000

Reexamination Certificate

active

10735113

ABSTRACT:
A method and system for striping across multiple cache lines to prevent false sharing. A first descriptor to correspond to a first data block is created. The first descriptor is placed in a descriptor ring according to a striping policy to prevent false sharing of a cache line of the computer system.

REFERENCES:
patent: 6389468 (2002-05-01), Muller et al.
patent: 6912602 (2005-06-01), Sano et al.
patent: 2002/0174252 (2002-11-01), Hayter et al.
David A. Patterson and John L. Hennessy, Computer Architecture A Quantitative Approach, 1996, Morgan Kaufmann Publishers, Inc., Second Edition, pp. 431-438.

Affiliated with

Also associated with

Rating

Striping across multiple cache lines to prevent false sharing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Striping across multiple cache lines to prevent false sharing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Striping across multiple cache lines to prevent false sharing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3847252