Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2009-03-31
2010-10-26
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S325000, C257S326000, C257SE29300, C257SE21179, C438S267000, C438S283000, C438S287000
Reexamination Certificate
active
07821055
ABSTRACT:
A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.
REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 6875660 (2005-04-01), Hung et al.
patent: 7235441 (2007-06-01), Yasui et al.
patent: 7436019 (2008-10-01), Lutze et al.
patent: 7446370 (2008-11-01), Chang et al.
patent: 7494860 (2009-02-01), Mokhlesi
patent: 7557402 (2009-07-01), Shyu et al.
patent: 2005/0104115 (2005-05-01), Kianian
patent: 2007/0132054 (2007-06-01), Arghavani et al.
patent: 2008/0042183 (2008-02-01), Mokhlesi
patent: 2008/0261385 (2008-10-01), Jawarani et al.
patent: 2009/0004796 (2009-01-01), Chang et al.
Arghavani et al; “Strain Engineering to Improve Data Retention Time in Non-Volatile memory”; IEEE Transactions on Electron Devices, vol. 54, No. 2, Feb. 2007.
Ortolland et al; “Stress Memorization Technique (SMT) Optimization for 45nm CMOS”; 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. pp. 78-79.
Ferri et al; “Influence of film thickness on the crystallization of Ni-doped amorphous silicon samples”; Journal of Applied Physics, vol. 104, 2008.
Zanatta et al; “Crystallization, stress, and stress-relieve due to nickel in amorphous silicon thin films”; Journal of Applied Physics, vol. 102, 2007.
Hong Cheong M.
Kang Sung-Taeg
Kirichenko Taras A.
Loiko Konstantin V.
Winstead Brian A.
Clingan, Jr. James L.
Fourson George
Freescale Semiconductor Inc.
Hill Daniel D.
LandOfFree
Stressed semiconductor device and method for making does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stressed semiconductor device and method for making, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stressed semiconductor device and method for making will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4194755