Stress test for memory arrays in integrated circuits

Details Stress test for memory arrays in integrated circuits Stress test for memory arrays in integrated circuits

1992-09-30

1995-06-13

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365202, G11C 700

Patent

active

054249880

ABSTRACT:
A method for stress testing a memory array in an integrated circuit. Control circuitry selects a plurality of row lines at one time. An overvoltage suitable for stressing the cells of the array is placed on the bit lines. Because a block of cells has been selected, the overvoltage is applied to all cells of the block. The block of cells selected may be either the entire memory array or a portion of the memory array. The selected rows remain selected for the duration of the stress test. Because the overvoltage is applied directly to selected cells, the full overvoltage will be used to stress the transistor gates for the entire test period. In this manner, latent defects within the memory array can be detected.

REFERENCES:
patent: 4342103 (1982-07-01), Higuchi
patent: 4651304 (1987-03-01), Takata
patent: 4751679 (1988-06-01), Dehganpour
patent: 5046049 (1991-09-01), Choi
patent: 5086413 (1992-02-01), Tsuboi
patent: 5208228 (1993-05-01), Kumanoya
patent: 5258954 (1993-11-01), Furuyama
patent: 5276647 (1994-01-01), Matsui

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