Stress shield for microelectronic dice

Details Stress shield for microelectronic dice Stress shield for microelectronic dice

2003-01-22

2004-08-31

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With stress relief

C257S676000, C257S677000

Reexamination Certificate

active

06784524

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and methods for fabricating microelectronic devices. In particular, the present invention relates to using a stress shield in the fabrication of microelectronic devices to reduce stress at corners and/or edges of microelectronic dice within the microelectronic devices.
2. State of the Art
As the size of electronic devices employing microelectronic dice continues to shrink and as the cost of such devices continues to fall, device manufacturers seek methods to incorporate microelectronic dice into their devices as efficiently as possible. The microelectronic dice should not require a large amount of space to mount, but must be securely and reliably affixed to their carrier substrates. The mounting method employed also should be as simple as possible, minimizing the time and equipment needed to mount the microelectronic dice to the substrates.
One mounting technology is called flip chip or C4 (“Controlled Collapse Chip Connection”) attachment, which is an inverted microelectronic die mounted to a substrate with a bumping process. As shown in
FIG. 8
a
, a flip chip
200
is a microelectronic die that has a pattern or array of terminations or bond pads
202
, generally metal or metal alloy pads, spaced on an active surface
204
of the flip chip
200
. An array of minute solder balls
206
, generally lead/tin solder, is disposed on the flip chip bond pads
202
, as shown in
FIG. 8
b.
The flip chip
200
is then positioned (i.e., flipped) such that the solder balls
206
are aligned with an array of bond pads
216
on an active surface
214
of a carrier substrate
212
, as shown in
FIG. 8
c
. The carrier substrate bond pads
216
are essentially in mirror-image placement to the flip chip bond pads
202
. It is, of course, understood that the solder balls
206
could be formed on the carrier substrate bond pads
216
, rather than the flip chip bond pads
202
. The solder balls
206
are then heated thereby reflowing them, such that when cooled the solder balls
206
solidify to form conductive pillars between the flip chip bond pads
202
and the carrier substrate bond pads
216
. An underflow material
218
is disposed between the flip chip
200
and the carrier substrate
212
to secure the flip chip
200
and to prevent possible contamination. This attachment technique is also used in C4 OLGA (“Organic Land Grid Array”) and FCPGA (“Flip Chip Pin Grid Array”) packages, as known in the art.
Another technology is called Chip-on-Flex (“COF”) packaging, which is shown in
FIGS. 9
a
-
9
d
. A flex component
232
(i.e., the carrier substrate) is attached with an adhesive layer
230
to an active surface
234
of microelectronic die
236
, as shown in
FIG. 9
a
. The microelectronic die active surface
234
includes at least one contact
238
. The microelectronic die
236
is then encapsulated with an encapsulating material
242
, such as plastics, resins, and the like, as shown in
FIG. 9
b
, that covers a back surface
244
and side(s)
246
of the microelectronic die
236
, and abuts a bottom surface
248
of the adhesive layer
230
(the portion not covered by the microelectronic die
236
).
As shown in
FIG. 9
c
, a plurality of conductive traces
254
are formed on an upper surface
256
of the flex component
232
and extend into vias
258
(formed through the flex component
232
and adhesive layer
230
) to contact the contacts
238
. The vias
258
may be formed by any known technique, but are general formed by laser ablation. The conductive traces
254
may also be formed by any known technique, such as photolithography.
As shown in
FIG. 9
d
, a plurality of additional flex component layers are stacked by attaching one atop another, represented by elements
232
′ and
232
″, with additional conductive traces formed thereon, represented by elements
254
′ and
254
″. A layer of solder resist
262
is then applied over the uppermost flex component layer and conductive traces, represented by elements
232
′ and
254
″, respectively. A plurality of vias
264
are formed through the solder resist layer
262
to expose a portion of the uppermost conductive trace, represented as element
254
″ and external contacts are formed on the conductive traces
254
″ (shown as solder balls
266
). The solder balls
266
may be attached to a substrate in a manner similar to flip chip attachment, as shown in
FIGS. 8
a
-
8
c.
Although the discussed techniques are widely used in the industry, the devices made from such techniques suffer from stress problems. The stresses are caused by a mismatch in the coefficients of thermal expansion (“CTE”) between the microelectronic dice and the packaging material (substrates, flex components, dielectric layers, etc.). These CTE induced stresses can cause mechanical damage including, but not limited to thin-film cracking and/or delamination, detachment of solder balls from the microelectronic die or the substrate, and cracking of the microelectronic dice. This problem can be lessened by excluding sensitive circuitry from the corners and/or edges of the microelectronic die. However, this approach is prohibitively expensive.
Therefore, it would be advantageous to develop an apparatus and technique to effectively achieve attachment of a microelectronic die to a supporting substrate, while eliminating or substantially reducing the potential for mechanical damage due to CTE mismatch.


REFERENCES:
patent: 5173764 (1992-12-01), Higgins, III
patent: 6147141 (2000-11-01), Iyer et al.
patent: 6214716 (2001-04-01), Akram
patent: 6300686 (2001-10-01), Hirano et al.
patent: 0 577 966 (1994-01-01), None

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