Stress relief matrix for integrated circuit packaging

Details Stress relief matrix for integrated circuit packaging Stress relief matrix for integrated circuit packaging

1999-01-21

2000-08-01

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

438119, H01L 2144

Patent

active

060965789

ABSTRACT:
An integrated circuit package (10, 40) may comprise an integrated circuit chip (12, 42) and a substrate (14, 44) opposite the chip (12, 42). A connector (20, 52) may be disposed between the chip (12, 42) and the substrate (14, 44) to electrically couple the chip (12, 42) and the substrate (14, 44). A matrix (24, 50) may be disposed about the connector (20, 52). The matrix (24, 50) may comprise a blend of liquid crystal polymer and thermoplastic polymer. The matrix (24, 50) may have a coefficient of thermal expansion in a direction (26, 56) substantially parallel to the chip (12, 42) and the substrate (14, 44) that is greater than that of the chip (12, 42) and that is less than that of the substrate (14, 44) in the substantially parallel direction (26, 56). In a direction (28, 58) normal to the substantially parallel direction (26, 56), the matrix (24, 50) may have a coefficient of thermal expansion that is approximately that of the connector (20, 52).

REFERENCES:
patent: 4825284 (1989-04-01), Soga et al.
patent: 4886686 (1989-12-01), Muenstedt
patent: 5364669 (1994-11-01), Sumida et al.
patent: 5553769 (1996-09-01), Ellerson et al.
patent: 5589236 (1996-12-01), Harvey et al.
patent: 5611140 (1997-03-01), Kulesza et al.
patent: 5656551 (1997-08-01), Corbett et al.
patent: 5659203 (1997-08-01), Call et al.
patent: 5709960 (1998-01-01), Mays
patent: 5783465 (1998-07-01), Canning et al.
patent: 5786238 (1998-07-01), Pai et al.
patent: 5863815 (1999-01-01), Egawa
Article from IEPS Conference, 1994, "Flip Chip Attachment Using Non-Conductive Adhesives and Gold Ball Bumps", pp. 794-807 (R. Aschenbrenner, J. Gwiasda, J. Eldring, E. Zakel and H. Reichl).
Article from IEEE, 1992, "Direct Chip Interconnect With Adhesive-Connector Films,"pp. 487-491 (Nagesh R. Basavanhally, David D. Chang, Benjamin H. Cranston).
Interpak 95 Proceedings, Hawaii, Mar. 1995, Reworkable Encapsulation for Flip-Chip Packaging, (Frank L. Pompeo, Anson J. Call, Jeffrey T. Coffin).

Affiliated with

Also associated with

Rating

Stress relief matrix for integrated circuit packaging does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stress relief matrix for integrated circuit packaging, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stress relief matrix for integrated circuit packaging will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-662875