Stress-relief layer for semiconductor applications

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S635000, C438S622000

Reexamination Certificate

active

06960835

ABSTRACT:
In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias.

REFERENCES:
patent: 2004/0227214 (2004-11-01), Hoinkis et al.

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