Stress released VLSI structure by void formation

Details Stress released VLSI structure by void formation Stress released VLSI structure by void formation

1996-05-29

1998-02-10

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438699, 438787, 438958, 438668, H01L 2156

Patent

active

057168881

ABSTRACT:
A new method of forming controlled voids within the intermetal dielectric and within the passivation layer of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the first patterned metal layer wherein the thickness of the intermetal dielectric layer is large enough so as to cause the formation of voids within the intermetal dielectric and wherein said voids are completely covered by said intermetal dielectric. A second layer of metallization is deposited over the intermetal dielectric and patterned. A passivation layer is deposited overlying the second patterned metal layer. The thickness of the passivation layer is large enough so as to cause the formation of voids within the passivation layer wherein said voids are completely covered by said passivation layer. The thermal stresses are released by the voids within the intermetal dielectric and within the passivation layer of the integrated circuit.

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