Stress reduction structure for a resin sealed semiconductor devi

Details Stress reduction structure for a resin sealed semiconductor devi Stress reduction structure for a resin sealed semiconductor devi

1990-05-01

1993-02-16

Larkins, William D.

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Physical deformation

257396, 257620, 257787, H01L 2328

Patent

active

051875586

ABSTRACT:
A resin sealed semiconductor device includes a semiconductor chip formed on a substrate and sealed with resin. A concave portion is formed on a major surface of a semiconductor substrate between an insulating film for isolation and an edge of the major surface of the semiconductor substrate. This concave portion is filled with a buffer member having an elastic modulus smaller than that of the material of the semiconductor substrate. Mechanical stress applied to an edge of the semiconductor substrate, caused by the callosity of resin, is absorbed and reduced by the buffer member. A portion of the semiconductor substrate between the concave portion and the insulating film for isolation prevents the remainder of the mechanical stress from being transmitted from the buffer member to the insulating film and circuit elements.

REFERENCES:
patent: 4453174 (1984-06-01), Kawasaki et al.
patent: 4481526 (1984-11-01), Miyasaka
patent: 4625227 (1986-11-01), Hara et al.
patent: 4799099 (1989-01-01), Verret et al.
patent: 4841354 (1989-06-01), Inaba
patent: 4903118 (1990-02-01), Iwade
patent: 4928162 (1990-05-01), Lesk et al.
patent: 4933744 (1990-06-01), Segawa et al.

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