Stress-managed revision of integrated circuit layouts

Details Stress-managed revision of integrated circuit layouts Stress-managed revision of integrated circuit layouts

2006-02-27

2009-10-06

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07600207

ABSTRACT:
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.

REFERENCES:
patent: 4998150 (1991-03-01), Rodder et al.
patent: 5854125 (1998-12-01), Harvey
patent: 5923947 (1999-07-01), Sur
patent: 6022781 (2000-02-01), Noble, Jr. et al.
patent: 6323113 (2001-11-01), Gabriel et al.
patent: 6664580 (2003-12-01), Jao et al.
patent: 6791155 (2004-09-01), Lo et al.
patent: 6826517 (2004-11-01), Okada
patent: 6831292 (2004-12-01), Currie et al.
patent: 6881632 (2005-04-01), Fitzgerald et al.
patent: 7032194 (2006-04-01), Hsueh et al.
patent: 7158401 (2007-01-01), Bhattacharyya
patent: 7190036 (2007-03-01), Ko et al.
patent: 7266787 (2007-09-01), Hughes et al.
patent: 2003/0173588 (2003-09-01), Bianchi
patent: 2005/0227440 (2005-10-01), Ema et al.
patent: 2006/0220142 (2006-10-01), Tamura
patent: 2007/0114632 (2007-05-01), Chidambarrao et al.
R.A. Bianchi et al., “Accurate Modeling of Trench Isolation Induced Mechanical Stress Effects on MOSFET Electrical Performance,” IEEE IEDM Tech. Digest, pp. 117-120 (Dec. 2002).
Xuemei (Jane) XI, et al., “BSIM4.3.0 Model, Enhancements and Improvements Relative to BSIM4.2.1 ”, University of California at Berkeley (2003) available at http://www-devices.eecs.berkeley.edu/—bsim3/BSIM4/BSIM430/doc/BSIM 430—Enhancement .pdf.
F. Nouri et al., “A Systematic Study of Trade-offs in Engineering a Locally Strained pMOSFET”, Proc. IEDM, pp. 1055-1058, 2004.
S.E. Thompson et al., “A 90-nm Logic Technology Featuring Strained-Silicon”, IEEE Transactions on Electron Devices, 2004.
G. Eneman et al, “Layout Impact on the Performance of a Locally Strained PMOSFET”, 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 22-23, 2005.
V. Moroz et al., “Analyzing strained-silicon options for stress-engineering transistors”, Solid State Technology, Jul. 2004.
Y. Kanda, “A Graphical Representation of the Piezoresistance Coefficients in Silicon”, IEEE Transactions on Electron Devices, vol. Ed-29, No. 1, Jan. 1982.
C.S. Smith, “Piezoresistance Effect in Germanium and Silicon”, Physical Review, vol. 94, No. 1, Apr. 1, 1954.
Smith, et al., “Exploring the Limits of Stress-Enhanced Hole Mobility”, IEEE Electron Device Letters, vol. 26, No. 9, Sep. 2005.
Moroz, et al., “Options at the 45 nm node include engineered substrates”, Solid State Technology, Jul. 2005.
C.P. Chang et al, “A Highly Manufacturable Corner Rounding Solution for 0.18μm Shallow Trench Isolation”, Bell Laboratories, Lucent Technologies, Murray Hill, NJ, 1997 IEEE, pp. 27.2.1 to 27.2.4.
C. Chen, et al, “A Novel 0.25 μm Shallow Trench Isolation Technology”, United Microelectronics Corp., Advanced Technology Develop. Dept., Hsin-Chu, Taiwan, R.O.C., 1996 IEEE.
Nirav Shah, “Stress Modeling of Nanoscale MOSFET”, a Thesis Presented to Graduate School of Univ. Of Florida., University of Florida, 2005.
Andres Bryant et al, “Characteristics of CMOS Device Isolation for the ULSI Age”, IBM Microelectronics Div., Siemens Components Inc., 1994 IEEE, pp. 28.1.1 to 28.1.5.
Loke, “Introduction to Deep Submicron CMOS Device Technology”, Powerpoint presentation, May 3, 2005, available at http://www.engr.colostate.edu.EE571/Files/2005—05—03—CSU.pdf, visited Oct. 4,2007.

Affiliated with

Also associated with

Rating

Stress-managed revision of integrated circuit layouts does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stress-managed revision of integrated circuit layouts, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stress-managed revision of integrated circuit layouts will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4080869