Stress isolating die attach structure and method

Details Stress isolating die attach structure and method Stress isolating die attach structure and method

2002-05-14

2004-11-23

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With stress relief

C257S689000, C257S712000, C257S733000, C438S106000, C438S123000

Reexamination Certificate

active

06822318

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to structures and techniques for attachment of a silicon die on a substrate, and more particularly relates to structures and techniques for reducing temperature- and pressure-induced stress on the die.
BACKGROUND OF THE INVENTION
To make a useful device of the electronic circuits fabricated onto silicon die, the die are usually packaged. For a variety of reasons, including cost, ease of fabrication, impact resistance, and so on, the package is not usually made out of silicon. Such packages are typically made of kovar or other metals and the silicon die is then rigidly bonded to that package. The portion of the package to which the die is bonded is sometimes referred to as the substrate or header.
The thermal coefficient of expansion for the silicon die is frequently very different than that for the header, which is usually much higher. This means that, when the temperature of the packaged die changes from that at which the die was bonded to the package, the dimensions of the package change more rapidly than the dimensions of the die and a thermal biomorph structure results. Stated more simply, the result is that the die is subjected to stress with a change in temperature, which can manifest either as warping or ‘in place’ stress. While this is not important for many types of electronic devices, such stress can adversely affect the performance of certain kinds of devices, including MEMS devices, accelerometers and pressure sensors. It has been observed that the most warping occurs when the silicon die and the package are of comparable thickness.
In the past, various techniques have been used to attempt to reduce thermally induced stress in such devices. One approach is to use a less rigid attachment of the die onto the substrate, such as by the use of silicone adhesives. This approach can result in greatly increased vibration and impact sensitivity, which is largely unacceptable in many applications. Another approach has been to bond the die onto a thick glass intermediate layer having a low expansion coefficient. The glass intermediate layer is then bonded to the header. In most instances, however, the glass is several times as thick as the silicon die or wafer, thus increasing the size of the package. In addition, while such glass intermediate layers increase the stiffness of the die, they do not appreciably reduce the bending moment applied to the glass-silicon bilayer.
Yet another approach has been to mount the die on a slotted metallic intermediate layer, such as described in U.S. Pat. No. 4,952,999. While this approach reduces the stress on the die, it does not increase the stiffness of the die, making it less effective than if both the stress was reduced and the stiffness increased.
Thus there has been a need for a structure which provided improved stress isolation as well as improved stiffness.
SUMMARY OF THE INVENTION
The present invention provides both increased die stiffness and materially improved stress isolation, without materially increased packaging size. In the present invention, the die is bonded to a silicon intermediate layer which has been relieved at specific points. The intermediate layer is then attached to the header at points which allow the relieved areas to absorb differential stresses, relative to the package, caused by thermal expansion. In particular, the die is typically bonded to the silicon intermediate layer essentially near the center of the die, and the silicon intermediate layer is then bonded to the header substantially at the perimeter of the intermediate layer. The relieved areas are typically intermediate the die attachment point(s) and the header attachment points, so that the relieved areas can flex to absorb any stresses induced by a change in dimensions of the package. While a silicon die and intermediate layer have been primarily described herein, it will be appreciated that the die and intermediate layer can be any semiconducting materials, with the intermediate layer being matched to the expansion index of the die.
In at least some embodiments, relief channels are cut into both the top and bottom of the wafer, and along both the length and the width thereof, with the result that the relief channels essentially form a rectangle around the die attachment area. As an additional feature, a second, more shallow series of channels may be cut interior of the relief channels to serve as reservoirs to prevent the adhesive used for bonding from flowing into the relief channels. Various patterns of channels may be used, depending on the particular device, and not every application will require relief channels on all sides of the die, just as not every application will require a rectangular shape to the channels. Likewise, not every application will require relief channels on the top and bottom of the die, although in general such an approach has been found more desirable.
The foregoing and other aspects of the invention may be better appreciated from the following Detailed Description of the Invention, taken together with the appended Figures.


REFERENCES:
patent: 3860949 (1975-01-01), Stoeckert et al.
patent: 5680385 (1997-10-01), Nagano

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