Stress enhanced semiconductor device and methods for...

Details Stress enhanced semiconductor device and methods for... Stress enhanced semiconductor device and methods for...

2007-09-25

2009-12-29

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S338000, C257S351000, C257S369000, C257SE27062

Reexamination Certificate

active

07638837

ABSTRACT:
A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.

REFERENCES:
patent: 7427544 (2008-09-01), Oishi
patent: 7442601 (2008-10-01), Pei et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2007/0202652 (2007-08-01), Moroz et al.
patent: 2009/0057729 (2009-03-01), Sultan et al.
Xiang-Zheng Bo et al., “Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors,” 2006 IEEE International SOI Conference Proceedings, 2 pages.

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