Streamlined write operation for EEPROM system

Details Streamlined write operation for EEPROM system Streamlined write operation for EEPROM system

1993-11-08

1995-03-07

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Erase

365185, 36518901, G11C 700

Patent

active

053964683

ABSTRACT:
Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; and adaptive initial erasing voltages. A streamlined write operation on a flash sector of the EEPROM is implemented by employing the optimized erase in an efficient manner. The write operation includes an initial quick erase of the sector followed by programming of data and verification. Only on those infrequent occasions when a failure occurs as manifested during program verification that the optimized erase will need be evoked.

REFERENCES:
patent: 4811294 (1989-03-01), Kobayashi et al.
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5214605 (1993-05-01), Lim et al.
patent: 5293560 (1994-03-01), Harari
patent: 5297095 (1994-03-01), Sato et al.

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