Streaming reads for early processing in a cascaded memory...

Details Streaming reads for early processing in a cascaded memory... Streaming reads for early processing in a cascaded memory...

2011-04-26

2011-04-26

Nguyen, Hiep T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

Reexamination Certificate

active

07934070

ABSTRACT:
A memory subsystem completes multiple read operations in parallel, utilizing the functionality of buffered memory modules in a daisy chain topology. A variable read latency is provided with each read command to enable memory modules to run independently in the memory subsystem. Busy periods of the memory device architecture are hidden by allowing data buses on multiple memory modules attached to the same data channel to run in parallel rather than in series and by issuing reads earlier than required to enable the memory devices to return from a busy state earlier. During scheduling of reads, the earliest received read whose target memory module is not busy is immediately issued at a next command cycle. The memory controller provides a delay parameter with each issued read. The number of cycles of delay is calculated to allow maximum utilization of the memory modules' data bus bandwidth without causing collisions on the memory channel.

REFERENCES:
patent: 7277988 (2007-10-01), Gower et al.
patent: 7337293 (2008-02-01), Brittain et al.
patent: 7389387 (2008-06-01), David
patent: 2002/0129215 (2002-09-01), Yoo et al.

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