Stream processor

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C710S029000, C710S033000, C710S038000

Reexamination Certificate

active

07054989

ABSTRACT:
The stream processor of the present invention includes: a selection section and first to fifth processing sections. In the selection section, a plurality of inputs are associated with a plurality of outputs according to control from outside so that streams sent to the plurality of inputs are passed to the associated outputs. The first processing section sends a first stream to the first input among the plurality of inputs. The second processing section sends a second stream to the second input among the plurality of inputs. The third processing section receives a stream from the first output among the plurality of outputs. The fourth processing section receives a stream from the second output among the plurality of outputs. The fifth processing section receives a stream from the third output among the plurality of outputs, subjects the received stream to predetermined processing, and sends the processed stream to the third input among the plurality of inputs.

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