Stratified charge ram having an opposite dopant polarity MOSFET

Static information storage and retrieval – Systems using particular element – Semiconductive

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365185, 357 23, 357 63, G11C 1140

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041582381

ABSTRACT:
A P-channel MOS stratified charge memory is formed on an N tub and controlled by peripheral N-channel MOS switches formed in the surrounding P substrate. A positive bias (+5 volts) applied to the N tub and a negative bias (-5 volts) applied to the P substrate create an isolation reverse bias therebetween. During the write mode, the row electrode of the addressed memory cell receives a positive control signal (+5 volts, zero with respect to the N tub) to establish accumulation for supporting electron conduction in the active channel under the row electrode. During the storage mode each row receives a less positive control signal (0 volts, minus five volts with respect to the N tub) to establish a depletion in the active channel thereunder which is nonconductive to both holes and electrons. During the read mode, the row of the addressed memory cell receives an even less positive control signal (-5 volts, minus ten volts with respect to the N tub) to establish inversion for supporting hole conduction in the active channel thereunder. The N dopant differential between the N+ doped row lead and the N doped active channel creates a work function slightly favorable towards electron accumulation during writing. In addition, the fixed positive surface charge (Qss) formed in the overlying gate oxide contributes toward electron accumulation. During the write mode when the row to tub voltage is zero, these two pro electron accumulation effects attract sufficient electrons from the N tub into the active channel to support the charging current into the memory storage region.

REFERENCES:
patent: 3996657 (1976-12-01), Simko et al.

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