Strategy to verify asynchronous links across chips

Details Strategy to verify asynchronous links across chips Strategy to verify asynchronous links across chips

2004-03-31

2008-12-09

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C703S013000, C703S014000, C703S015000

Reexamination Certificate

active

07464287

ABSTRACT:
Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

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