Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – With lattice constant mismatch
Reexamination Certificate
2004-06-16
2009-02-24
Sefer, A. (Department: 2893)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
With lattice constant mismatch
C257S019000, C257S020000, C257S024000, C257S191000, C257S192000, C257SE21232, C257SE21284, C257SE21546
Reexamination Certificate
active
07495266
ABSTRACT:
A semiconductor-based structure includes first and second layers bonded directly to each other at an interface. Parallel to the interface, the lattice spacing of the second layer is different than the lattice spacing of the first layer. The first and second layers are each formed of essentially the same semiconductor. A method for making a semiconductor-based structure includes providing first and second layers that are formed of essentially the same semiconductor. The first and second layers have, respectively, first and second surfaces. The second layer has a different lattice spacing parallel to the second surface than the lattice spacing of the first layer parallel to the first surface. The method includes contacting the first and second surfaces, and annealing to promote direct atomic bonding between the first and second layers.
REFERENCES:
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 6893936 (2005-05-01), Chen et al.
patent: 6924181 (2005-08-01), Huang et al.
patent: 7202530 (2007-04-01), Forbes
patent: 2002/0140031 (2002-10-01), Rim
patent: 2003/0030091 (2003-02-01), Bulsara et al.
patent: 2004/0026765 (2004-02-01), Currie et al.
patent: 2004/0074866 (2004-04-01), Fournel et al.
patent: 2004/0217352 (2004-11-01), Forbes
patent: 2005/0020094 (2005-01-01), Forbes et al.
patent: 2005/0104067 (2005-05-01), Chu et al.
patent: 2005/0202604 (2005-09-01), Cheng et al.
patent: 2005/0230676 (2005-10-01), Bae et al.
patent: 2005/0247926 (2005-11-01), Sun et al.
patent: 2005/0250294 (2005-11-01), Ghyselen
patent: 2001-291864 (2001-10-01), None
patent: WO 99/53539 (1999-10-01), None
patent: WO 0100522 (2001-01-01), None
patent: WO 01/99169 (2001-12-01), None
patent: WO 03/094239 (2003-11-01), None
patent: WO 2004/000632 (2004-01-01), None
patent: WO 2004/002142 (2004-03-01), None
Zhixiong Liu et al., “Micromechanism Fabrication using Silicon Fusion Bonding,” Robotics and Computer Integrated manufacturing 17, 2001, pp. 131-137.
A.C. Gracias et al., “Experiments on Silicon-To-Silicon Direct Bonding,” XIII Meeting of the Brazilian Vacuum Society, Campinas, Brazil, Jul. 1998, pp. 19-22.
International Search Report PCT/US2005/021283, dated Oct. 28, 2005.
Langdo et al., “SiGe-Free Strained Si on Insulator by Wafer Bonding and Layer Transfer,” Applied Physics Letters, Jun. 16, 2003, pp. 4256-4257, vol. 82, No. 24, American Institute of Physics, Melville, NY, US.
Taraschi, et al., “Relaxed SiGe-on-insulator fabricated via wafer bonding and etch back,” Journal of Vacuum Science and Technology, Mar. 2002, pp. 725-726, vol. 20, No. 2, American Institute of Physics, New York, NY, US.
Pitera et al., “Coplanar Integration of Lattice-Mismatched Semiconductors with Silicon by Wafer Bonding Ge/Sil-xGex/Si Virtual Substrates,” Feature Article ISSN 0013-4651, 2004, pp. G443-447, vol. 151, No. 7, Journal of The Electrochemical Society, Inc.
Taraschi et al., “Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques,” Feature Article ISSN 0038-1101, 2004, pp. 1297-1305, vol. 48, Solid-State Electronics.
Taraschi et al., “Ultrathin Strained Si-on-Insulator and SiGe-on-Insulator Created using Low Temperature Wafer Bonding and Metastable Stop Layers,” Feature Article ISSN 0013-4651, 2004, pp. G47-G56, vol. 151, No. 1, Journal of The Electrochemical Society, Inc.
Erratum of B9, Journal of Materials Science Materials in Electronics ISSN 0957-4522, Oct. 2002, p. 621, vol. 13, No. 10.
Cheng et al., “Relaxed silicon-germanium on insulator substrate by layer transfer,” Feature Article, Dec. 2001, pp. L37-39, vol. 30, No. 12, Journal of Electronic Materials.
Currie, et al., “Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates,” Journal of Vacuum Science & Technology, Nov. 2001, pp. 2268-2279, vol. 19, No. 6, American Vacuum Society.
Lee et al., “Strained Ge channelp-type metal-oxide-semiconductor field-effect transistors grown on Si1-xGEx/ Si virtual substrates,” Applied Physics Letters, Nov. 12, 2001, pp. 3344-3346, vol. 79, No. 20, American Institute of Physics.
Cheng et al., “Electron mobility enhancement in strained-Si n-MOSFETs fabricated on SiGe-on-insulator (SGOI) substrates,” IEEE Electronic Device Letters, Jul. 2001, pp. 321-323, vol. 22, No. 7.
Sieg et al., “High minority-carrier lifetimes in GaAs grown on low-defect-density Ge/GeSi/Si substrates,” Applied Physics Letters, Nov. 23, 1998, pp. 3111-3113, vol. 73, No. 21, American Institute of Physics.
Taraschi et al., “Strained-Si-on-Insulator (SSOI) and SiGe-on-Insulator (SGOI): Fabrication obstacles and Solutions,” Symposium, Dec. 2-4, 2002, pp. 105-110, vol. 745, Material Identity No. XX-2003-01738, Mater. Res. Soc. Symposium Proceedings.
Gianni Taraschi, “Strained Si-on-insulator development accelerates,” Journal: Compound Semiconductor, ISSN 1096-598X, Apr. 2003, pp. 25-27, vol. 9, No. 3, Franklin Publishing, US.
Lee et al., “Strained Ge channelp-type MOSFETs fabricated on Si1-xGEx//Si virtual substrates,” Symposium, Nov. 26-28, 2001, pp. 39-43, vol. 686, Mater. Res. Soc., Warrendale, PA, US.
Cheng et al., “Relaxed silicon-germanium on insulator (SGOI),” Symposium, Nov. 26-28, 2001, pp. 21-26, vol. 686, Mater. Res. Soc., Warrendale, PA, US.
Taraschi et al., “Relaxed SiGe on insulator fabricated via wafer bonding and layer transfer: Etch-back and smart-cut alternatives,” Proceedings of the Tenth International Symposium (Electrochemical Society Proceedings), Mar. 25-29, 2001, pp. 27-32, vol. 2001-3, Electrochemical Soc., Pennington, NJ, US.
Cheng et al., “SiGe-on-Insulator (SGOI): substrate preparation and MOSFET fabrication for electron mobility evaluation,” Conference: 2001 IEEE International SOI Conference, Oct. 1-4, 2001, pp. 13-14, Cat. No. 01CH37207, IEEE, Piscataway, NJ, US.
Fitzgerald et al., “Dislocations in relaxed SiGe/Si heterostructures,” International Conference on Extended Defects in Semiconductors (EDS'98), Sep. 6-11, 1998, pp. 227-238, vol. 171, No. 1, Journal: Physica Status Solidi A, Wiley-VCH, Germany.
Fitzgerald Eugene A.
Isaacson David M.
Massachusetts Institute of Technology
Sefer A.
Wolf Greenfield & Sacks P.C.
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