Strained silicon-on-insulator transistors with mesa isolation

Details Strained silicon-on-insulator transistors with mesa isolation Strained silicon-on-insulator transistors with mesa isolation

2007-01-02

2007-01-02

Blum, David S. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S351000

Reexamination Certificate

active

10356036

ABSTRACT:
A silicon-on-insulator semiconductor device which includes a substrate; and insulator layer overlying the substrate; a plurality of strained silicon islands overlying the insulator layer, the strained silicon islands are isolated from each other by mesa isolation; and a plurality of transistors formed on the strained silicon islands. A method for fabricating the silicon-on-insulator semiconductor device is further disclosed.

REFERENCES:
patent: 6521510 (2003-02-01), Fisher et al.
patent: 6624478 (2003-09-01), Anderson et al.
patent: 6727550 (2004-04-01), Tezuka et al.
patent: 2002/0140031 (2002-10-01), Rim
patent: 2004/0018668 (2004-01-01), Maszara

Affiliated with

Also associated with

Rating

Strained silicon-on-insulator transistors with mesa isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Strained silicon-on-insulator transistors with mesa isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Strained silicon-on-insulator transistors with mesa isolation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3797804