Strained silicon NMOS having silicon source/drain extensions...

Details Strained silicon NMOS having silicon source/drain extensions... Strained silicon NMOS having silicon source/drain extensions...

2005-03-15

2005-03-15

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

C257S018000, C257S020000, C257S192000, C257S200000, C257S616000

Reexamination Certificate

active

06867428

ABSTRACT:
An n-type strained silicon MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon regions are provided in the silicon geranium layer at opposing sides of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon regions. By forming the shallow source and drain extensions in silicon regions rather than in silicon germanium, source and drain extension distortions caused by the enhanced diffusion rate of arsenic in silicon germanium are avoided.

REFERENCES:
patent: 6583000 (2003-06-01), Hsu et al.
patent: 6657223 (2003-12-01), Wang et al.
patent: 20020123197 (2002-09-01), Fitzgerald et al.
patent: 20020125497 (2002-09-01), Fitzgerald
patent: 20030068883 (2003-04-01), Ajmera et al.
patent: 20030139001 (2003-07-01), Snyder et al.
patent: 20040061191 (2004-04-01), Paton et al.
patent: 20040097025 (2004-05-01), Fitzgerald

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