Strained silicon-channel MOSFET using a damascene gate process

Details Strained silicon-channel MOSFET using a damascene gate process Strained silicon-channel MOSFET using a damascene gate process

2005-07-12

2005-07-12

Chaudhari, Chandra (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S530000, C438S938000

Reexamination Certificate

active

06916694

ABSTRACT:
The present invention provides a method using a damascene-gate process to improve the transport properties of FETs through strain Si. Changes in mobility and FET characteristics are deliberately made in a Si or silicon-on-insulator (SOI) structure through the introduction of local strain in the channel region, without introducing strain in the device source and drain regions. The method has the advantage of not straining the source and drain regions resulting in very low leakage junctions and also it does not require any special substrate preparation like the case of a strained Si/relaxed SiGe system. Moreover, the method is compatible with existing mainstream CMOS processing. The present invention also provides a CMOS device that has a localized strained Si channel that is formed using the method of the present invention.

REFERENCES:
patent: 4514895 (1985-05-01), Nishimura
patent: 6310367 (2001-10-01), Yagishita et al.
patent: 6593191 (2003-07-01), Fitzgerald

Affiliated with

Also associated with

Rating

Strained silicon-channel MOSFET using a damascene gate process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Strained silicon-channel MOSFET using a damascene gate process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Strained silicon-channel MOSFET using a damascene gate process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3398897