Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2007-01-02
2007-01-02
Norton, Nadine (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S718000, C438S767000
Reexamination Certificate
active
10669063
ABSTRACT:
A method for in situ formation of low defect, strained silicon and a device formed according to the method are disclosed. In one embodiment, a silicon germanium layer is formed on a substrate, and a portion of the silicon germanium layer is removed to expose a surface that is smoothed with a smoothing agent. A layer of strained silicon is formed on the silicon germanium layer. In various embodiments, the entire method is conducted in a single processing chamber, which is kept under vacuum.
REFERENCES:
patent: 6107653 (2000-08-01), Fitzgerald
patent: 2002/0197803 (2002-12-01), Leitz et al.
patent: 2004/0067644 (2004-04-01), Malik et al.
patent: 1085562 (2001-03-01), None
patent: 1085562 (2001-03-01), None
patent: WO 01/54202 (2001-07-01), None
Notification of transmittal of the international search report and the written opinion of the international search suthority, or the declaration, PCT/US2004/030504, Apr. 1, 2005.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Norton Nadine
Tran Binh X.
LandOfFree
Strained semiconductor structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Strained semiconductor structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Strained semiconductor structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3757735