Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2009-09-17
2010-11-02
Hoang, Quoc D (Department: 2892)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257SE29193
Reexamination Certificate
active
07825401
ABSTRACT:
A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same. The at least one strained transitional layer reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer relative to CTE contraction of the substrate.
REFERENCES:
patent: 5442205 (1995-08-01), Brasen et al.
patent: 5445897 (1995-08-01), Satoh et al.
patent: 5633516 (1997-05-01), Mishima et al.
patent: 5847409 (1998-12-01), Nakayama
patent: 6154475 (2000-11-01), Soref et al.
patent: 6350993 (2002-02-01), Chu et al.
patent: 6525338 (2003-02-01), Mizushima et al.
patent: 6573126 (2003-06-01), Cheng et al.
patent: 6953736 (2005-10-01), Ghyselen et al.
patent: 7022593 (2006-04-01), Arena et al.
patent: 7049627 (2006-05-01), Vineis et al.
patent: 7357838 (2008-04-01), Lin et al.
patent: 7390725 (2008-06-01), Maa et al.
patent: 7402504 (2008-07-01), Brabant et al.
patent: 7608526 (2009-10-01), Cody et al.
patent: 2003/0153161 (2003-08-01), Chu et al.
patent: 2003/0157787 (2003-08-01), Murthy et al.
patent: 2003/0230233 (2003-12-01), Fitzgerald et al.
patent: 2004/0075105 (2004-04-01), Leitz et al.
patent: 2004/0087117 (2004-05-01), Leitz et al.
patent: 2004/0157409 (2004-08-01), Ghyselen et al.
patent: 2004/0178406 (2004-09-01), Chu
patent: 2004/0192002 (2004-09-01), Soman et al.
patent: 2004/0219735 (2004-11-01), Brabant et al.
patent: 2005/0051795 (2005-03-01), Arena et al.
patent: 2005/0054175 (2005-03-01), Bauer
patent: 2005/0150447 (2005-07-01), Ghyselen et al.
patent: 2005/0170577 (2005-08-01), Yao et al.
patent: 2005/0191826 (2005-09-01), Bauer et al.
patent: 2006/0145188 (2006-07-01), Dantz et al.
patent: 2007/0048956 (2007-03-01), Dip et al.
patent: 2007/0264801 (2007-11-01), Cody et al.
patent: 2008/0017952 (2008-01-01), Cody et al.
patent: 1 681 711 (2006-07-01), None
Bolkhovityanov et al., “Artificial GeSi Substrates for Heteroepitaxy: Achievements and Problems,”Semiconductors37(5): 493-518 (2003).
Fitzgerald et al., “Totally Relaxed GexSi1-xLayers with Low Threading Dislocation Densities Grown on Si Substrates,”Appl. Phys. Lett. 59(7): 811-813 (1991).
Isella et al., “Low-energy plasma-enhanced chemical vapor deposition for strained Si and Ge heterostructures and devices” Solid State Electronics, Elsevier Science Publishers, Barking, GB, vol. 48, No. 8, Aug. 2004, pp. 1317-1323.
Levinshtein et al.,Properties of Advanced Semiconductor Materials GaN, AIN, InN, BN, SiC, SiGe, John Wiley & Sons, Inc., 149-187 (2001).
Obata et al., “Structural Characterization of Si0.7Ge0.3Layers Grown on Si(001) Substrates by Molecular Beam Epitaxy,”J. Appl. Phys. 81(1): 199-204 (1997).
Presting et al., “Buffer Concepts of Ultrathin SimGenSuperlattices” Thin Solid Films, Elsevier-Sequoia S.A. Lausanne, CH, vol. 222, No. 1/2, pp. 215-220 (1992).
Yamamoto et al., “Dislocation Structures and Strain-Relaxation in SiGe Buffer Layers on Si (0 0 1) Substrates with an Ultra-Thin Ge Interlayer,”Appl. Surface Sci. 224: 108-112 (2004).
Pending U.S. Appl. No. 11/267,494, entitled: Semiconductor Heterostructure and Method for Forming a Semiconductor Heterostructure, filed Mar. 11, 2005 by Christophe Figuet and Mark Kennard.
Pending U.S. Appl. No. 11/146,572, entitled: Laminated Layer Structure and Method for Forming the Same, filed Jun. 6, 2005 by Christophe Figuet.
International Search Report and Written Opinion for PCT Application No. PCT/US2007/072252 dated Dec. 19, 2007.
International Preliminary Report on Patentability for International Application No. PCT/US2007/072252, dated Nov. 3, 2008.
Restriction Requirement dated Mar. 9, 2009, received in U.S. Appl. No. 11/491,616, filed Jul. 24, 2006.
Notice of Allowance dated Jul. 9, 2009, received in U.S. Appl. No. 11/491,616, filed Jul. 24, 2006.
Singapore Search Report dated Jun. 16, 2009, received in Singapore Application No. 200809179-5, filed Jun. 27, 2007.
Singapore Written Opinion dated Jun. 16, 2009, received in Singapore Application No. 200809179-5, filed Jun. 27, 2007.
Cody Nyles W.
Figuet Christophe
Kennard Mark
ASM America Inc.
Hoang Quoc D
Knobbe Martens Olson & Bear LLP
S.O.I. Tec Silicon On Insulator Technologies, S.A.
LandOfFree
Strained layers within semiconductor buffer structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Strained layers within semiconductor buffer structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Strained layers within semiconductor buffer structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4201614