Storing results of resolvable branches during speculative...

Details Storing results of resolvable branches during speculative... Storing results of resolvable branches during speculative...

2005-03-29

2009-02-10

Patel, Niketa I (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Branching

Reexamination Certificate

active

07490229

ABSTRACT:
One embodiment of the present invention provides a system that facilitates storing results of resolvable branches during speculative execution, and then using the results to predict the same branches during non-speculative execution. During operation, the system executes code within a processor. Upon encountering a stall condition, the system speculatively executes the code from the point of the stall, without committing results of the speculative execution to the architectural state of the processor. Upon encountering a branch instruction that is resolved during speculative execution, the system stores the result of the resolved branch in a branch queue, so that the result can be subsequently used to predict the branch during non-speculative execution.

REFERENCES:
patent: 5687110 (1997-11-01), Tran et al.
patent: 2001/0037447 (2001-11-01), Mukherjee et al.
patent: 2004/0225870 (2004-11-01), Srinivasan et al.
patent: WO 03/040916 (2003-05-01), None
“Execution-based Prediction Using Speculative Slices”; Zilles et al.; IEEE; 2001.
“Checkpoint Repair for Out-of-order Execution Machines”; Hwu et al.; ACM; 1987.
Publication entitled “A Study Slipstream Processors”, by Zach Purser et al., ASPLOS, 2000, pp. 269-280.
Publication entitled “Speculative Data-Driven Multithreading” by Amir Roth et al., HPCA '01, 2001, pp. 37-48.

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