Storing data to multi-chip low-latency random read memory...

Details Storing data to multi-chip low-latency random read memory... Storing data to multi-chip low-latency random read memory...

2011-04-15

2011-12-27

Trimmings, John (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S770000, C714S774000, C714S769000, C714S006130, C714S006120, C714S006220, C714S006230, C714S006240, C365S185010, C365S185090, C365S200000, C365S201000

Reexamination Certificate

active

08086914

ABSTRACT:
Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

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