Store instruction ordering for multi-core processor

Details Store instruction ordering for multi-core processor Store instruction ordering for multi-core processor

2004-11-30

2009-10-20

Kindred, Alford W (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

C712S220000

Reexamination Certificate

active

07606998

ABSTRACT:
A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue.

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