Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-08-05
2001-06-19
Robertson, David (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000, C712S205000
Reexamination Certificate
active
06249843
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a data processing in general, and in particular to a STORE instruction to be utilized within a data processing system. Still more particularly, the present invention relates to a STORE instruction having horizontal memory hierarchy control bits to be utilized within a multiprocessor data processing system.
2. Description of the Prior Art
Typically, Reduced Instruction Set Computing (RISC) processors have fewer instructions than their Complex Instruction Set Computing (CISC) counterparts. Thus, to a certain extent, RISC technology simplifies the task of writing compilers for processors that utilize a RISC instruction set. Moreover, from a processor design standpoint, focus can be placed on implementing and optimizing those important and frequently-used instructions rather than having some complex but seldom-used instructions constrain the maximum operating efficiency. Because of the above-mentioned reasons and others, RISC processors are gaining popularity among workstation and even some lower-end computer manufacturers.
For RISC processors, it is common that very few instructions are actually memory access instructions. In fact, some implementations may have only two instructions, LOAD and STORE, that access memories. Typically, a few specialized “atomic” operations may also be supported by the RISC processor for synchronization and memory updates via concurrent processes. Even in such cases, LOAD and STORE instructions are by far the most frequently-used memory access instructions for RISC processors. The execution of a LOAD instruction will cause a processor register to be written with data associated with in a specified main memory address. Conversely, the execution of a STORE instruction will cause data resident in a processor register to be written to a memory hierarchy in association with a main memory address. The present invention is related to a STORE instruction for updating data within a memory hierarchy of multiprocessor data processing system.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a STORE instruction comprises an operation code field, a write-through field, and a horizontal write-through level field. The horizontal write-through level field indicates a horizontal memory level within a multi-level memory hierarchy to which the STORE operation should be applied, when the write-through field is set.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Arimilli Ravi Kumar
Dodson John Steve
Guthrie Guy Lynn
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Robertson David
Salys Casimer K.
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