Store-induced instruction coherency mechanism

Details Store-induced instruction coherency mechanism Store-induced instruction coherency mechanism

2007-08-28

2007-08-28

Bataille, Pierre (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S125000, C711S141000, C711S205000, C711S207000

Reexamination Certificate

active

10665171

ABSTRACT:
An apparatus and method for ensuring coherency of instructions within stages of the pipeline microprocessor. The apparatus includes instruction cache management logic and synchronization logic. The instruction cache management logic receives an address corresponding to a next instruction to be fetched, and detects that a part of a memory page corresponding to the next instruction cannot be freely accessed without checking for coherency of the instructions within the part of the memory page and, upon detection, provides the address. The synchronization logic receives the address from the instruction cache management logic. The synchronization logic directs data cache management logic to check for coherency of the instructions within the part of the memory page, and, if the instructions are not coherent within the part of the memory page, the synchronization logic directs the pipeline microprocessor to stall a fetch of the next instruction until the stages of the pipeline.

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