Store buffer apparatus with two store buffers to increase throug

Details Store buffer apparatus with two store buffers to increase throug Store buffer apparatus with two store buffers to increase throug

1996-10-15

1998-12-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711100, 711117, 711122, G06F 1200, G06F 1300

Patent

active

058453210

ABSTRACT:
A store buffer apparatus connected to a CPU and a main storage unit includes a first buffer for holding a pair of store address and store data in the main storage unit supplied from an operation execution unit of the CPU, a first latch connected to the first buffer means for holding the store address, a second latch connected to the first latch for holding an output of the first latch, a judgment device for comparing an output read out from the address array with an output of the second latch to thereby judge whether the cache hit check for the store address is successful or not and a second buffer for holding the pair of store data and store address having successful cache hit check judged by the judgment device. Occurrence of the state that the store buffer is full is reduced. Two data stored in the second buffer can possess a format into which the two data can be merged.

REFERENCES:
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patent: 5426749 (1995-06-01), Morioka
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patent: 5544340 (1996-08-01), Doi
patent: 5564034 (1996-10-01), Miyake
patent: 5644748 (1997-07-01), Utsunomiya et al.
patent: 5659709 (1997-08-01), Quach

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