Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-01-29
2008-01-29
Kerveros, James C. (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S725000
Reexamination Certificate
active
07325179
ABSTRACT:
The storage system includes a PLD (Programmable Logic Device), which controls data transfer between another device and a media drive; and a processor. The PLD includes a memory for storing information input from an information source located externally to the PLD; a circuit element group including a plurality of circuit elements; and a logical circuit configured on the circuit element group in accordance with the information in the memory. The processor detects whether a soft error has occurred in the memory, detects whether or not an error has occurred in the logical circuit, and implements control in accordance with the results of the two detection operations.
REFERENCES:
patent: 6009548 (1999-12-01), Chen et al.
patent: 2006/0117234 (2006-06-01), Miyake et al.
patent: 8-137764 (1996-05-01), None
Hitachi , Ltd.
Kerveros James C.
Mattingly ,Stanger ,Malur & Brundidge, P.C.
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